Corstone-101

hello I want to know how to reset axi master can cause axi bus  matrix deadlock in soc design,and how to aviod or detect this condition? I use nic400 matrix bus.

When I am reading 'ARM' ® CoreLink SIE-200 System IP for Embedded "Technical Reference Manual. Regarding the AHB5 exclusive access monitor, there is a paragraph that reads: Can it be understood as ' hexokay_m signal is tied 0 'in the following figure? Because during integration, the hexokay_m signal is the signal input from external devices to the AHB5 exclusive access monitor module. But my external device did not do any additional logic to generate hexokay_m signals. If the AHB5 exclusive access monitor module of CoreLink  SIE-200 System IP is used, Can the hexokay_m signal is tied 0 ?

I'm trying to understand how I would be able to connect a Mali-G78AE to the CMN-600AE.  The I/O coherent requester nodes are able to support 3 channels each and the G78AE can have up to 8 ACE-Lite connections depending on the number of slices.  Are you able to use multiple nodes for one device or do they have to be connected to another network connector so that they can all be connected to a single port.  I assume that these were tested and mean to be used together so I'm trying to understand how this is typically done.  Any thoughts are helpful.  Thank you!