Reference design subsystem and system IP for building a secure System on Chip (SoC)
The Arm Corstone-101 contains a reference design based on the Cortex-M3 processor and various other system IP components. It also contains the Cortex-M System Design Kit which provides all the fundamental system elements to design an SoC around Arm Cortex-M0, Cortex-M0+, Cortex-M3 and Cortex-M4 processor.
- The fastest way to incorporate the Cortex-M3 processor into an SoC design.
- Example systems for Cortex-M0, Cortex-M0+, Cortex-M3, and Cortex-M4 processors.
- A selection of AMBA AHB and APB infrastructure components.
- Embedded Flash controllers by providing a simple interface between the system and the Flash.
The following diagram illustrates the Corstone-101 reference design (SSE-050 subsystem) integration and build:
Corstone SSE-050 subsystem
The SSE-050 subsystem delivers a pre-integrated and validated reference design based around the Cortex-M3 processor. It consists of a processor, an associated bus, debug, and expansion and interface logic provided by Arm. It is modifiable and expandable, ready to connect your external peripheral to design your custom solution. The SSE-050 expansion ports allow you to have a very high level of flexibility, making the SSE-050 subsystem a great start for your next SoC.
The Corstone-101 combines software and hardware components for Cortex-M based designs.
The components include:
The Cortex-M System Design Kit (CMSDK) includes:
- A selection of AMBA AHB and APB infrastructure components
- Essential peripherals such as GPIO, timers, watchdog, and UART
- Example systems for Cortex-M0, Cortex-M0+, Cortex-M3, and Cortex-M4 processors
- Compilation and simulation scripts for the Verilog environment
- Software drivers and example programs
Cortex-M System Design Kit System example
The CMSDK provides example AMBA systems to bring the designer to a working system as quickly as possible, offering a library of fundamental peripherals and interconnect generation with software drivers and examples.
The CMSDK Example Systems differ significantly from the reference design subsystems. For example the SSE-050 reference design is developed to an Arm defined architecture, pre-integrated and fully verified. The SSE-050 is used as the basis of an IoT SoC using the Cortex-M3 processor.
The CMSDK example systems however are intended to be used in two ways:
- As a learning tool to understand how to integrate the CMSDK components with Armv6-M and Armv7-M processors.
- To be used as a validation (out-of-the-box) testbench to show that every CMSDK component works and behaves as expected according to configuration of each module. The example system is not intended to be used as a verification testbench.
An example system for Cortex-M0 and Cortex-M0+ is shown in the following diagram:
The example system supports many configuration options, for example:
- DMA option – if the Arm CoreLink DMA-230 DMA controller is licensed you can plug in the DMA controller and use it in the system immediately. You can also modify the design to use your own DMA controller.
- Bit band wrapper – if the system requires bit band compatibility with Cortex-M3 or Cortex-M4 this functionality can be included.
- Boot ROM – this option demonstrates how to design a system with boot loader ROM in addition to the user program memory, for example Flash.
It is straightforward to extend the example system and plug in other peripheral designs. For designers new to AMBA, the example AHB and APB slaves are a good starting point for your design.
An example system for Cortex-M3 and Cortex-M4 processors is also included, as the following diagram shows:
The Cortex-M3 or Cortex-M4 system has the same memory map and interrupt assignments as the Cortex-M0 and M0+ system. It also uses the same AMBA APB subsystem as the Cortex-M0 and Cortex-M0+ example. Again, the integration of the DMA controller and boot loader are optional.
The Cortex-M System Design Kit consists of the following components:
|APB components||Advanced AHB-Lite components||The memory models||The verification components|
|APB example slave||AHB bus matrix||ROM model wrapper||AHB-Lite protocol checker|
|APB timer||AHB upsizer||RAM model wrapper||APB protocol checker|
|APB UART||AHB downsizer||Behavioral SRAM model with AHB interface||AHB File Reader Bus Master (FRBM)|
|APB dual timer||AHB to APB asynchronous bridge||32-bit Flash ROM behavioral model|
|APB watchdog||AHB to AHB and APB asynchronous bridge||16-bit Flash ROM behavioral model|
|APB slave multiplexer||AHB to AHB synchronous bridge||SRAM synthesizable (for FPGA) model|
|APB subsystem||AHB to AHB sync-down bridge||FPGA ROM|
|APB timeout monitor||AHB to AHB sync-up bridge||External asynchronous 8-bit SRAM|
|External asynchronous 16-bit SRAM|
AHB Flash Cache
To get the most of Flash-based systems (either with embedded Flash or external Flash), an efficient cache system is necessary. Within a compact area, this block significantly improves performance and power consumption of your SoC.
A Real-Time Clock (RTC) for applications that must maintain a time base, which is likely to be the case for all embedded applications.
True Random Number Generator
The True Random Number Generator (TRNG) is the minimum element that you must integrate into a device to ensure a strong security foundation.