Overview

Reference design and system IP for building a secure System on Chip (SoC) with the Cortex-M33 processor

The Corstone-201 contains various system IP components and a reference design subsystem integrating the processor, memory, debug, security, and power control. It is designed for mainstream IoT and embedded applications that require power efficiency and performance.

Corstone-201 provides:

  • The fastest way to incorporate the Cortex-M33 into an SoC design.
  • System-wide implementation of TrustZone technology making chip-level security easier and faster to integrate.
  • Simplified software development with support from Arm’s comprehensive software ecosystem.
  • Silicon proven with FPGA and Fast Models available.

The following diagram illustrates the Corstone-201 reference design (SSE-200 subsystem) integration and build:

SSE-200 block diagram

Corstone SSE-200 subsystem
The SSE-200 subsystem is a fully verified implementation of a dual-core Cortex-M33-based subsystem architecture. It integrates many features, which can be viewed in more detail below. The SSE-200 subsystem is fully verified, extensible, and comes with full modification rights.

Building security into an embedded system and integrating all the necessary components take a significant amount of time and effort. The SSE-200 subsystem aims to make this difficult process easier, by integrating and validating Arm IP in one system.

A dual-core system allows the background OS to run on the energy-efficient processor, while the second high-performance processor can be used for more demanding tasks. This partitioning delivers significant performance bursts while keeping the average power consumption very low.

Caches have also been integrated in the system to reduce power consuming accesses to the Flash. The always-on domain allows the application to powerdown the system while keeping synchronization.

The SSE-200 subsystem integrates the following Arm IP:

  • Arm Cortex-M33 processor
  • Arm CoreLink SIE-200
  • Instruction caches with Arm TrustZone support
  • Power infrastructure components
  • CoreSight SoC-400M
  • Arm CryptoCell (option)

Features

The Corstone-201 combines all of the necessary hardware elements for Cortex-M33-based designs.
The components include:

CoreSight SDC-600
CoreSight SDC-600 addresses device security needs by allowing silicon and tool vendors to enforce protection and to police debug access, and by working closely with cryptographic elements and debug certificate authentication.

CoreLink SIE-200 System IP
Includes all the components required to create TrustZone-enabled systems. For example, AHB5 interconnect generator, memory and peripheral protection controllers, bridges, and more.

CoreLink GFC-100
CoreLink Generic Flash Controller (GFC-100) enables an embedded Flash macro to be integrated easily into any system.

CoreLink GFC-200
Similar to GFC-100, but the GFC-200 can have accesses from two masters. The two masters can operate in separate domains, such as a Non-secure domain and a Secure domain.

CoreLink PCK-600 Power Control
The Arm CoreLink PCK-600 Power Control Kit provides a suite of system IP that is pre-verified to ease system power, and clock management infrastructure integration.

AHB Flash Cache
To get the most of Flash-based systems (either with embedded Flash or external Flash), an efficient cache system is necessary. Within a compact area, this block significantly improves performance and power consumption of your SoC.

Real-Time Clock
A Real-Time Clock (RTC) for applications that must maintain a time base, which is likely to be the case for all embedded applications.

True Random Number Generator
The True Random Number Generator (TRNG) is the minimum element that you must integrate into a device to ensure a strong security foundation.

Other components included with Corstone-201: