A reference package for building Linux-capable System on Chips (SoCs)
The Arm Corstone-500 offers a subsystem and associated System IP for building a high-performance Linux-capable SoC, based on the Arm Cortex-A5 processor. There is a stripped-down variant of Corstone-500 available - namely Corstone-500 Preconfigured. This variant does not include few system IP.
For early software prototyping Corstone-500 offers a Fixed Virtual Platform (FVP) and FPGA-based implementation on the MPS3 board. Both platforms are supported by an open-source software Linux stack.
The following diagram shows an example integration layer of the Corstone-500:
The following components are included in Corstone-500:
CoreLink Level 2 Cache Controller L2C-310
The addition of an on-chip secondary cache, also referred to as a Level 2 or L2 cache, is a recognized method of improving the performance of Arm-based systems when the processor generates significant memory traffic. The cache controller is a unified, physically addressed, physically tagged cache with up to 16 ways.
CoreSight SoC-400 solution for debug and trace
CoreSight SoC-400 is a comprehensive library of components for the creation of debug and trace functionality within a system. This IP is not included in the Corstone-500 Preconfigured. A preconfigured instance of the IP is available in SSE-500 subsystem.
CoreLink NIC-400 Network Interconnect
The NIC-400 enables you to create a complete high performance, optimized, and AMBA-compliant network infrastructure. The infrastructure can range from a single bridge component to a complex interconnect of up to 128 requesters and 64 subordinates of AMBA protocols. This IP is not included in the Corstone-500 Preconfigured. A preconfigured instance of the IP is available in SSE-500 subsystem.
True Random Number Generator
The True Random Number Generator (TRNG) provides an assured level of entropy (as analyzed by Entropy Estimation logic). You can use the output from the TRNG to seed deterministic random bit generators.
Real Time Clock
The Real Time Clock (RTC) is an AMBA slave module that connects to the Advanced Peripheral Bus (APB). A 1Hz clock input to the RTC generates counting in one second intervals. The RTC provides an alarm function or long-time base counter by generating an interrupt signal after counting a programmed number of cycles of the clock input.
The UART is an Advanced Microcontroller Bus Architecture (AMBA) compliant SoC peripheral that is developed, tested, and licensed by Arm. The UART is an AMBA subordinate module that connects to the Advanced Peripheral Bus (APB). The UART includes an Infrared Data Association (IrDA) on Serial InfraRed (SIR) protocol ENcoder/DECoder (ENDEC).
PrimeCell general-purpose input and output
The PrimeCell GPIO is an AMBA bus slave that connects to the AMBA APB. It provides eight programmable inputs or outputs that you can control in either software or hardware modes.
PrimeCell synchronous serial port
The PrimeCell Synchronous Serial Port (SSP) is an AMBA completer block that connects to the APB. The PrimeCell SSP is an AMBA-compliant SoC peripheral that is developed, tested, and licensed by Arm.
If the watchdog is not refreshed within a certain time, it raises an interrupt signal. The watchdog uses the Generic Timer system counter as the time base against which the decision to trigger an interrupt is made. Watchdog provides the capability of system recovery.