Getting Started

Arm CoreLink Interconnect provides the components and the methodology for designers to build SoCs based on the latest Arm AMBA specifications, maximizing the efficiency of data movement and storage, delivering the performance needed at the lowest power and cost. There are three CoreLink Interconnect families, each optimized for their target applications. High performance SoCs with multiple processor clusters would include a Cache Coherent Interconnect, combined with CoreLink Network Interconnect to provide connectivity for the whole SoC.

Highest Performance Coherency

CoreLink Coherent Mesh Network Chip.

CoreLink Coherent Mesh Network

  • Designed for scaling to the highest performance infrastructure applications including networking and servers.
  • Offering scalable system coherency in multi-core heterogeneous processor systems.
  • Highly configurable and scalable CoreLink CMN-600.
  • Previous generation: CoreLink CCN-512, CCN-508, CCN-504 and CCN-502.
  • Find out more CMN.
  • Find out more CCN.

Highest Efficiency Coherency

CoreLink Cache Coherent Interconnects

CoreLink Cache Coherent Interconnect

  • Optimized for the highest efficiency coherent applications including mobile big.LITTLE processing.
  • Offering the smallest and lowest power multi-cluster interconnect.
  • Family consists of: CoreLink CCI-550, CCI-500, CCI-400.
  • Find out more.

Network on Chip (NoC)    

CoreLink Network Interconnect Family

CoreLink Network Interconnect

  • Fully configurable for SoC connectivity across all applications.
  • Hierarchical, low latency and low power connectivity.
  • Back plane for smaller, single processor designs.
  • Companion interconnect for I/O coherency and rest of SoC connectivity with CoreLink CCI and CCN.
  • Family consists of: CoreLink NIC-450, NIC-400 and NIC-301.
  • Find out more.

CoreLink Interconnect Family Comparison

Product CoreLink CMN-600 and
CoreLink CCN Family
CoreLink CCI Family CoreLink NIC Family
Summary Scalable range of high performance, power efficient coherent interconnects targeting network infrastructure and servers.
Configurable interconnect for power and area sensitive applications including mobile big.LITTLE processing, set top box, digital TV, automotive and low cost network infrastructure.
Low latency interconnect for rest of System on Chip (SoC) connectivity, or single cluster processing such as wearables or embedded.
Processors Up to 32 clusters (128 cores) Up to 6 clusters (24 cores) or CPU and GPU coherency Configurable, non-coherent
AMBA Interface AMBA 5 CHI AMBA 4 ACE and AXI4 AMBA 4 AXI4, AXI3, AHB-Lite, APB
Bus Width 128-bit or 256-bit transport
128-bit Configurable 32-bit to 256-bit
Memory Channels 1-8 Channels up to x64-bit 1-6 Channels up to x32-bit
Configurable
I/O Interfaces Up to 96 AXI4 / ACE-Lite interfaces
Up to 0-6 ACE-Lite
Connects multiple devices to CCI and CCN
 

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Answered How could I find the critical functions when dual core cpu is fully loading?
  • AArch64
  • embedded linux
  • performance analysis
  • Armv8-A
  • DS-5 Community Edition
0 votes 139 views 2 replies Latest 3 days ago by Myles Answer this
Answered when I choosed the Debugger 'Connect only', the Debug can not click 0 votes 385 views 4 replies Latest 13 days ago by Ven Answer this
Answered Debug component part numbers
  • debugger
0 votes 456 views 4 replies Latest 21 days ago by Juha Aaltonen Answer this
Answered ARMCC: How to generate assembly
  • GNU GCC
0 votes 2418 views 8 replies Latest 24 days ago by Holly R. Malin Answer this
Answered How can I debug two A53 cores in DS-5 tool
  • Cortex-A53
  • Arm Development Studio
  • DS-5 Debugger
  • Debugging
0 votes 306 views 3 replies Latest 25 days ago by Ronan Synnott Answer this
Answered How to analyze critical function(in kernel module) that caused CPU-bound task by streamline?
  • AArch64
  • Kernel Developers
  • performance analysis
  • Streamline Performance Analyzer
0 votes 227 views 1 replies Latest 1 months ago by Jason Andrews Answer this
Answered How could I find the critical functions when dual core cpu is fully loading? Latest 3 days ago by Myles 2 replies 139 views
Answered when I choosed the Debugger 'Connect only', the Debug can not click Latest 13 days ago by Ven 4 replies 385 views
Answered Debug component part numbers Latest 21 days ago by Juha Aaltonen 4 replies 456 views
Answered ARMCC: How to generate assembly Latest 24 days ago by Holly R. Malin 8 replies 2418 views
Answered How can I debug two A53 cores in DS-5 tool Latest 25 days ago by Ronan Synnott 3 replies 306 views
Answered How to analyze critical function(in kernel module) that caused CPU-bound task by streamline? Latest 1 months ago by Jason Andrews 1 replies 227 views