Getting Started

Arm CoreLink Interconnect provides the components and the methodology for designers to build SoCs based on the latest Arm AMBA specifications, maximizing the efficiency of data movement and storage, delivering the performance needed at the lowest power and cost. There are three CoreLink Interconnect families, each optimized for their target applications. High performance SoCs with multiple processor clusters would include a Cache Coherent Interconnect, combined with CoreLink Network Interconnect to provide connectivity for the whole SoC.

CoreLink Coherent Mesh Network

CoreLink Coherent Mesh Network Chip.  

  • Designed for scaling to the highest performance infrastructure applications including networking and servers.
  • Offering scalable system coherency in multi-core heterogeneous processor systems.
  • Highly configurable and scalable CoreLink CMN-600.
  • Previous generation: CoreLink CCN-512, CCN-508, CCN-504 and CCN-502.

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Learn more CCN

CoreLink Cache Coherent Interconnect

CoreLink Cache Coherent Interconnects 

  • Optimized for the highest efficiency coherent applications including consumer smartphones.
  • Offering the smallest and lowest power multi-cluster interconnect.
  • Family consists of: CoreLink CI-700, CCI-550, CCI-500, CCI-400.

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CoreLink Network Interconnect

CoreLink Network Interconnect Family 

  • Fully configurable for SoC connectivity across all applications.
  • Hierarchical, low latency and low power connectivity.
  • Back plane for smaller, single processor designs.
  • Companion interconnect for I/O coherency and rest of SoC connectivity with CoreLink CCI and CCN.
  • Family consists of: CoreLink NIC-700, NIC-450, NIC-400 and NIC-301.

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CoreLink Interconnect Family Comparison

Product CoreLink CMN-600 and
CoreLink CCN Family
CoreLink CCI Family CoreLink NIC Family
Summary Scalable range of high performance, power efficient coherent interconnects targeting network infrastructure and servers.
Configurable interconnect for power and area sensitive applications including mobile big.LITTLE processing, set top box, digital TV, automotive and low cost network infrastructure.
Low latency interconnect for rest of System on Chip (SoC) connectivity, or single cluster processing such as wearables or embedded.
Processors Up to 32 clusters (128 cores) Up to 6 clusters (24 cores) or CPU and GPU coherency Configurable, non-coherent
AMBA Interface AMBA 5 CHI AMBA 4 ACE and AXI4 AMBA 4 AXI4, AXI3, AHB-Lite, APB
Bus Width 128-bit or 256-bit transport
128-bit Configurable 32-bit to 256-bit
Memory Channels 1-8 Channels up to x64-bit 1-6 Channels up to x32-bit
Configurable
I/O Interfaces Up to 96 AXI4 / ACE-Lite interfaces
Up to 0-6 ACE-Lite
Connects multiple devices to CCI and CCN
 

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Learn more CCN

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Answered Where is main.c file located in Keil uVision 5?
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Answered NCONT ERROR in ACK when running debug on DE10-Nano
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Answered STM32L100RC - CDC device
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Answered Failed to load "<project>.axf" - ERROR (CMD16-TAD274-NAL22) - Can't run bare-metal application from SDRAM. Latest 5 days ago by elliots 5 replies 815 views
Answered Can't read project project file 'ProjectFileName'! Latest 8 days ago by rkopsch 19 replies 9253 views
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Answered Code Coverage in Keil Latest 14 days ago by rkopsch 5 replies 420 views
Answered NCONT ERROR in ACK when running debug on DE10-Nano Latest 14 days ago by elliots 3 replies 268 views
Answered STM32L100RC - CDC device Latest 16 days ago by Andy Neil 5 replies 386 views