Getting Started

Arm CoreLink Interconnect provides the components and the methodology for designers to build SoCs based on the latest Arm AMBA specifications, maximizing the efficiency of data movement and storage, delivering the performance needed at the lowest power and cost. There are three CoreLink Interconnect families, each optimized for their target applications. High performance SoCs with multiple processor clusters would include a Cache Coherent Interconnect, combined with CoreLink Network Interconnect to provide connectivity for the whole SoC.

Highest Performance Coherency

CoreLink Coherent Mesh Network Chip.

CoreLink Coherent Mesh Network

  • Designed for scaling to the highest performance infrastructure applications including networking and servers.
  • Offering scalable system coherency in multi-core heterogeneous processor systems.
  • Highly configurable and scalable CoreLink CMN-600.
  • Previous generation: CoreLink CCN-512, CCN-508, CCN-504 and CCN-502.
  • Find out more about CMN.
  • Find out more about CCN.

Highest Efficiency Coherency

CoreLink Cache Coherent Interconnects

CoreLink Cache Coherent Interconnect

  • Optimized for the highest efficiency coherent applications including mobile big.LITTLE processing.
  • Offering the smallest and lowest power multi-cluster interconnect.
  • Family consists of: CoreLink CCI-550, CCI-500, CCI-400.
  • Find out more.

Network on Chip (NoC)    

CoreLink Network Interconnect Family

CoreLink Network Interconnect

  • Fully configurable for SoC connectivity across all applications.
  • Hierarchical, low latency and low power connectivity.
  • Back plane for smaller, single processor designs.
  • Companion interconnect for I/O coherency and rest of SoC connectivity with CoreLink CCI and CCN.
  • Family consists of: CoreLink NIC-450, NIC-400 and NIC-301.
  • Find out more.

CoreLink Interconnect Family Comparison

Product CoreLink CMN-600 and
CoreLink CCN Family
CoreLink CCI Family CoreLink NIC Family
Summary Scalable range of high performance, power efficient coherent interconnects targeting network infrastructure and servers.
Configurable interconnect for power and area sensitive applications including mobile big.LITTLE processing, set top box, digital TV, automotive and low cost network infrastructure.
Low latency interconnect for rest of System on Chip (SoC) connectivity, or single cluster processing such as wearables or embedded.
Processors Up to 32 clusters (128 cores) Up to 6 clusters (24 cores) or CPU and GPU coherency Configurable, non-coherent
AMBA Interface AMBA 5 CHI AMBA 4 ACE and AXI4 AMBA 4 AXI4, AXI3, AHB-Lite, APB
Bus Width 128-bit or 256-bit transport
128-bit Configurable 32-bit to 256-bit
Memory Channels 1-8 Channels up to x64-bit 1-6 Channels up to x32-bit
Configurable
I/O Interfaces Up to 96 AXI4 / ACE-Lite interfaces
Up to 0-6 ACE-Lite
Connects multiple devices to CCI and CCN
 

Learn more CMN
Learn more CCN

Learn more

Learn more


Get support

Community Forums

Answered Product license check-out for feature "platform_editor:202003" failed
  • ARM Development Suite (ADS)
  • DSTREAM
0 votes 236 views 2 replies Latest 21 hours ago by David DV Answer this
Answered If I don't see any events in the EvenRecorder other than the initialization, does it mean that the RTOS is not running?
  • uVision
0 votes 302 views 2 replies Latest 2 days ago by coldspark Answer this
Answered Locating large data blocks in LPC4078 SRAM 0 votes 325 views 2 replies Latest 2 days ago by TdeP Answer this
Answered What does this message mean? osRtxInfo not found
  • uVision
0 votes 509 views 3 replies Latest 6 days ago by Adam Lins Answer this
Answered Problems with setting up the event recorder for LPC1769
  • Cortex-M
  • event
0 votes 1024 views 11 replies Latest 7 days ago by coldspark Answer this
Answered Can only step through assembly code and not the C/C++ editor
  • Debugger
0 votes 421 views 4 replies Latest 7 days ago by coldspark Answer this
Answered Product license check-out for feature "platform_editor:202003" failed Latest 21 hours ago by David DV 2 replies 236 views
Answered If I don't see any events in the EvenRecorder other than the initialization, does it mean that the RTOS is not running? Latest 2 days ago by coldspark 2 replies 302 views
Answered Locating large data blocks in LPC4078 SRAM Latest 2 days ago by TdeP 2 replies 325 views
Answered What does this message mean? osRtxInfo not found Latest 6 days ago by Adam Lins 3 replies 509 views
Answered Problems with setting up the event recorder for LPC1769 Latest 7 days ago by coldspark 11 replies 1024 views
Answered Can only step through assembly code and not the C/C++ editor Latest 7 days ago by coldspark 4 replies 421 views