CoreLink CCI-400

The Arm CoreLink CCI-400 Cache Coherent Interconnect

Premium Mobile CCI400 System Diagram.

Getting Started

The Arm CoreLink CCI-400 Cache Coherent Interconnect provides full cache coherency between two clusters of multi-core CPUs. It enables big.LITTLE processing and I/O coherency for devices such as the Mali-T600 series GPU, and I/O masters like modem and USB. First released in 2011, CoreLink CCI-400 has been widely licensed and is today shipping in many millions of production devices.

CoreLink CPE-425 Coherent PCIe Extension for CCI-400

The Arm CPE-425 Coherent PCIe Extension for Corelink CCI-400 is a companion product available through Flexible Access. A small overview of the extension:

  • A companion product for Corelink CCI-400
  • Enables IO Coherent PCIe for Corelink CCI-400
  • Allows CPU write backs to flow, removing known deadlocks and terminating barriers

Specifications

 Features Details
 AMBA Specifications
 AMBA 4 ACE and ACE-Lite
 ACE Slave interfaces 2 for fully coherent processors including Arm Cortex
 ACE-Lite slave interfaces 1-3 for IO coherent devices such as Mali processors, accelerators and IO
 Memory and System master interfaces

1-2 memory interfaces
1 system interface
 Coherency
 Broadcast snoop protocol
 Memory map 40 bit Physical, configurable address map
44 bit DVM

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

Learn more

  • TRM

  • CoreLink CCI-400 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    CCI-400 TRM
  • A guide on software optimization.

  • AMBA 4 ACE Specification

    CoreLink CCI-400 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs
  • A program that is running on a desktop.

  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.


    Learn more

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Community Forums

Answered Forum FAQs
  • ARM Community
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Answered Forum FAQs
  • ARM Community
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Answered ethernet sample code 0 votes 1016 views 9 replies Latest 3 days ago by SRIDHAR R Answer this
Not answered APB - Purpose of PADDR?
  • APB
  • APB Peripherals
  • AMBA 3 APB Interface
  • AMBA 2 APB Interface
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Suggested answer Need help to choose MCU 0 votes 687 views 3 replies Latest 5 days ago by Oliver Beirne Answer this
Not answered Does it use a Slow Clock to turn off Main Clock? 0 votes 100 views 0 replies Started 11 days ago by Ridge Mao Answer this
Answered Forum FAQs Started 1 months ago by Annie Cracknell 0 replies 2876 views
Answered Forum FAQs Started 1 months ago by Annie Cracknell 0 replies 2887 views
Answered ethernet sample code Latest 3 days ago by SRIDHAR R 9 replies 1016 views
Not answered APB - Purpose of PADDR? Started 3 days ago by Kyle Kochan 0 replies 62 views
Suggested answer Need help to choose MCU Latest 5 days ago by Oliver Beirne 3 replies 687 views
Not answered Does it use a Slow Clock to turn off Main Clock? Started 11 days ago by Ridge Mao 0 replies 100 views