CoreLink CCI-400

The Arm CoreLink CCI-400 Cache Coherent Interconnect

Premium Mobile CCI400 System Diagram.

Getting Started

The Arm CoreLink CCI-400 Cache Coherent Interconnect provides full cache coherency between two clusters of multi-core CPUs. It enables big.LITTLE processing and I/O coherency for devices such as the Mali-T600 series GPU, and I/O masters like modem and USB. First released in 2011, CoreLink CCI-400 has been widely licensed and is today shipping in many millions of production devices.

Specifications

 Features Details
 AMBA Specifications
 AMBA 4 ACE and ACE-Lite
 ACE Slave interfaces 2 for fully coherent processors including Arm Cortex
 ACE-Lite slave interfaces 1-3 for IO coherent devices such as Mali processors, accelerators and IO
 Memory and System master interfaces

1-2 memory interfaces
1 system interface
 Coherency
 Broadcast snoop protocol
 Memory map 40 bit Physical, configurable address map
44 bit DVM

  • TRM

  • CoreLink CCI-400 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    CCI-400 TRM
  • A guide on software optimization.

  • AMBA 4 ACE Specification

    CoreLink CCI-400 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs
  • A program that is running on a desktop.

  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.



    Learn more

Resources

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Community Forums

Answered ACE protocol : Eviction and snoop request at same time
  • AMBA
  • l1
  • ACE
  • cache
 0 votes 334 views 1 replies Latest 6 days ago by Christopher Tory Answer this
Suggested answer AXI3 write data interleaving with same AWID
  • AMBA
  • AXI
 0 votes 398 views 4 replies Latest 7 days ago by mveereshm622 Answer this
Suggested answer AHB revisions from AHB3 to AHB5
  • AMBA
  • AHB
 0 votes 148 views 1 replies Latest 7 days ago by Colin Campbell Answer this
Suggested answer Burst termination with BUSY transfer on AHB
  • AMBA
  • AHB
 0 votes 127 views 1 replies Latest 7 days ago by Colin Campbell Answer this
Suggested answer Regarding retry response
  • AMBA
  • AHB
 0 votes 119 views 1 replies Latest 7 days ago by Colin Campbell Answer this
Suggested answer APB3 Slave responding when PSEL = 0
  • APB
  • AMBA
 0 votes 322 views 2 replies Latest 12 days ago by vshankar11 Answer this
Answered ACE protocol : Eviction and snoop request at same time Latest 6 days ago by Christopher Tory 1 replies 334 views
Suggested answer AXI3 write data interleaving with same AWID Latest 7 days ago by mveereshm622 4 replies 398 views
Suggested answer AHB revisions from AHB3 to AHB5 Latest 7 days ago by Colin Campbell 1 replies 148 views
Suggested answer Burst termination with BUSY transfer on AHB Latest 7 days ago by Colin Campbell 1 replies 127 views
Suggested answer Regarding retry response Latest 7 days ago by Colin Campbell 1 replies 119 views
Suggested answer APB3 Slave responding when PSEL = 0 Latest 12 days ago by vshankar11 2 replies 322 views