CoreLink CCI-400

The Arm CoreLink CCI-400 Cache Coherent Interconnect

Premium Mobile CCI400 System Diagram.

Getting Started

The Arm CoreLink CCI-400 Cache Coherent Interconnect provides full cache coherency between two clusters of multi-core CPUs. It enables big.LITTLE processing and I/O coherency for devices such as the Mali-T600 series GPU, and I/O masters like modem and USB. First released in 2011, CoreLink CCI-400 has been widely licensed and is today shipping in many millions of production devices.

Specifications

 Features Details
 AMBA Specifications
 AMBA 4 ACE and ACE-Lite
 ACE Slave interfaces 2 for fully coherent processors including Arm Cortex
 ACE-Lite slave interfaces 1-3 for IO coherent devices such as Mali processors, accelerators and IO
 Memory and System master interfaces

1-2 memory interfaces
1 system interface
 Coherency
 Broadcast snoop protocol
 Memory map 40 bit Physical, configurable address map
44 bit DVM

  • TRM

  • CoreLink CCI-400 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    CCI-400 TRM
  • A guide on software optimization.

  • AMBA 4 ACE Specification

    CoreLink CCI-400 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs
  • A program that is running on a desktop.

  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.



    Learn more

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Community Forums

Suggested answer boundary concept
  • AMBA
  • AXI
  • AHB
 0 votes 304 views 3 replies Latest yesterday by harrykayn Answer this
Suggested answer State Machine for AHB-Lite Protocol
  • ahb-lite
  • AHB
 0 votes 177 views 3 replies Latest 4 days ago by Colin Campbell Answer this
Suggested answer Amba Adaptive Traffic Profiles question
  • AMBA
 0 votes 111 views 1 replies Latest 6 days ago by Matteo Maria Andreozzi Answer this
Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?
  • AXI
 0 votes 185 views 2 replies Latest 7 days ago by Zax Answer this
Suggested answer Assertion for Multiple Transfer on APB Bus
  • APB
  • AMBA
  • Bus Architecture
 0 votes 127 views 2 replies Latest 8 days ago by Rakesh Venkatesan Answer this
Answered What purpose do wrapping BURST transfers serve?
  • ahb-lite
  • AHB
 0 votes 150 views 1 replies Latest 8 days ago by Colin Campbell Answer this
Suggested answer boundary concept Latest yesterday by harrykayn 3 replies 304 views
Suggested answer State Machine for AHB-Lite Protocol Latest 4 days ago by Colin Campbell 3 replies 177 views
Suggested answer Amba Adaptive Traffic Profiles question Latest 6 days ago by Matteo Maria Andreozzi 1 replies 111 views
Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst? Latest 7 days ago by Zax 2 replies 185 views
Suggested answer Assertion for Multiple Transfer on APB Bus Latest 8 days ago by Rakesh Venkatesan 2 replies 127 views
Answered What purpose do wrapping BURST transfers serve? Latest 8 days ago by Colin Campbell 1 replies 150 views