CoreLink CCI-400

The Arm CoreLink CCI-400 Cache Coherent Interconnect

Premium Mobile CCI400 System Diagram.

Getting Started

The Arm CoreLink CCI-400 Cache Coherent Interconnect provides full cache coherency between two clusters of multi-core CPUs. It enables big.LITTLE processing and I/O coherency for devices such as the Mali-T600 series GPU, and I/O masters like modem and USB. First released in 2011, CoreLink CCI-400 has been widely licensed and is today shipping in many millions of production devices.


CoreLink CPE-425 Coherent PCIe Extension for CCI-400 Diagram

CoreLink CPE-425 Coherent PCIe Extension for CCI-400

The Arm CPE-425 Coherent PCIe Extension for Corelink CCI-400 is a companion product available through Flexible Access. A small overview of the extension:

  • A companion product for Corelink CCI-400
  • Enables IO Coherent PCIe for Corelink CCI-400
  • Allows CPU write backs to flow, removing known deadlocks and terminating barriers

Specifications

 Features Details
 AMBA Specifications
AMBA 4 ACE and ACE-Lite
 ACE Slave interfaces 2 for fully coherent processors including Arm Cortex
 ACE-Lite slave interfaces 1-3 for IO coherent devices such as Mali processors, accelerators and IO
 Memory and System master interfaces

1-2 memory interfaces
1 system interface

 Coherency
Broadcast snoop protocol
 Memory map 40 bit Physical, configurable address map
44 bit DVM

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.


  • TRM
  • CoreLink CCI-400 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    CCI-400 TRM
  • A guide on software optimization.
  • AMBA 4 ACE Specification

    CoreLink CCI-400 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs
  • A program that is running on a desktop.
  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.


    Learn more

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Suggested answer APB4 PSTRB 0 votes 126 views 1 replies Latest 19 hours ago by Colin Campbell Answer this
Answered how to calculate unaligned address for APB? 0 votes 10644 views 7 replies Latest yesterday by Ravi V. Answer this
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Suggested answer Porting to U-boot driver model and device tree control (for ARM-based design)
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Not answered Ulink pro debugging in custom SoC
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0 votes 193 views 0 replies Started 12 days ago by ronit Answer this
Not answered C9912E: --cpu selected 0 votes 237 views 0 replies Started 13 days ago by -C9912E: No --cpu selected Answer this
Suggested answer APB4 PSTRB Latest 19 hours ago by Colin Campbell 1 replies 126 views
Answered how to calculate unaligned address for APB? Latest yesterday by Ravi V. 7 replies 10644 views
Suggested answer AHB Lite Latest 2 days ago by Colin Campbell 1 replies 1129 views
Suggested answer Porting to U-boot driver model and device tree control (for ARM-based design) Latest 8 days ago by rwl 1 replies 2382 views
Not answered Ulink pro debugging in custom SoC Started 12 days ago by ronit 0 replies 193 views
Not answered C9912E: --cpu selected Started 13 days ago by -C9912E: No --cpu selected 0 replies 237 views