CoreLink CCI-400

The Arm CoreLink CCI-400 Cache Coherent Interconnect

Premium Mobile CCI400 System Diagram.

Getting Started

The Arm CoreLink CCI-400 Cache Coherent Interconnect provides full cache coherency between two clusters of multi-core CPUs. It enables big.LITTLE processing and I/O coherency for devices such as the Mali-T600 series GPU, and I/O masters like modem and USB. First released in 2011, CoreLink CCI-400 has been widely licensed and is today shipping in many millions of production devices.

Specifications

 Features Details
 AMBA Specifications
 AMBA 4 ACE and ACE-Lite
 ACE Slave interfaces 2 for fully coherent processors including Arm Cortex
 ACE-Lite slave interfaces 1-3 for IO coherent devices such as Mali processors, accelerators and IO
 Memory and System master interfaces

1-2 memory interfaces
1 system interface
 Coherency
 Broadcast snoop protocol
 Memory map 40 bit Physical, configurable address map
44 bit DVM

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

Learn more

  • TRM

  • CoreLink CCI-400 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    CCI-400 TRM
  • A guide on software optimization.

  • AMBA 4 ACE Specification

    CoreLink CCI-400 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs
  • A program that is running on a desktop.

  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.



    Learn more

Resources

Get support

Community Forums

Not answered I am working on protocol checker VC of APB4 to which I have to test the assertions written. Does it mean I have to write test cases to verify my assertions? 0 votes 107 views 0 replies Started yesterday by aditya raja Answer this
Not answered My application code is not working when i load its bin file through uart into the flash and jump to the address of the application code (custom bootloader)
  • Cortex-M0
 0 votes 64 views 0 replies Started yesterday by aarushi Answer this
Not answered Inconsistency in latest AXI4 specification (version g) regarding INCR burst transfers.
  • AXI4
 0 votes 190 views 0 replies Started 3 days ago by MuchToLearn Answer this
Suggested answer AXI4 master requirements for unaligned transactions (address v/s WSTRB) 0 votes 456 views 1 replies Latest 3 days ago by guimers8 Answer this
Not answered TFT/LCD graphic contoller 0 votes 375 views 0 replies Started 4 days ago by levetop Answer this
Not answered Missing CoreSight components in /renensas/r8a77970.dtsi
  • CoreSight Trace Funnel
  • replicator
  • TPIU
  • AMBA 3 ATB Interface
  • CoreSight System Trace Macrocell (STM)
 0 votes 359 views 0 replies Started 4 days ago by LWT Answer this
Not answered I am working on protocol checker VC of APB4 to which I have to test the assertions written. Does it mean I have to write test cases to verify my assertions? Started yesterday by aditya raja 0 replies 107 views
Not answered My application code is not working when i load its bin file through uart into the flash and jump to the address of the application code (custom bootloader) Started yesterday by aarushi 0 replies 64 views
Not answered Inconsistency in latest AXI4 specification (version g) regarding INCR burst transfers. Started 3 days ago by MuchToLearn 0 replies 190 views
Suggested answer AXI4 master requirements for unaligned transactions (address v/s WSTRB) Latest 3 days ago by guimers8 1 replies 456 views
Not answered TFT/LCD graphic contoller Started 4 days ago by levetop 0 replies 375 views
Not answered Missing CoreSight components in /renensas/r8a77970.dtsi Started 4 days ago by LWT 0 replies 359 views