CoreLink CCI-400

The Arm CoreLink CCI-400 Cache Coherent Interconnect

Premium Mobile CCI400 System Diagram.

Getting Started

The Arm CoreLink CCI-400 Cache Coherent Interconnect provides full cache coherency between two clusters of multi-core CPUs. It enables big.LITTLE processing and I/O coherency for devices such as the Mali-T600 series GPU, and I/O masters like modem and USB. First released in 2011, CoreLink CCI-400 has been widely licensed and is today shipping in many millions of production devices.

CoreLink CPE-425 Coherent PCIe Extension for CCI-400

The Arm CPE-425 Coherent PCIe Extension for Corelink CCI-400 is a companion product available through Flexible Access. A small overview of the extension:

  • A companion product for Corelink CCI-400
  • Enables IO Coherent PCIe for Corelink CCI-400
  • Allows CPU write backs to flow, removing known deadlocks and terminating barriers

Specifications

 Features Details
 AMBA Specifications
 AMBA 4 ACE and ACE-Lite
 ACE Slave interfaces 2 for fully coherent processors including Arm Cortex
 ACE-Lite slave interfaces 1-3 for IO coherent devices such as Mali processors, accelerators and IO
 Memory and System master interfaces

1-2 memory interfaces
1 system interface
 Coherency
 Broadcast snoop protocol
 Memory map 40 bit Physical, configurable address map
44 bit DVM

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

Learn more

  • TRM

  • CoreLink CCI-400 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    CCI-400 TRM
  • A guide on software optimization.

  • AMBA 4 ACE Specification

    CoreLink CCI-400 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs
  • A program that is running on a desktop.

  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.


    Learn more

Get support

Community Forums

Answered Forum FAQs
  • ARM Community
 0 votes 5556 views 0 replies Started 8 months ago by Annie Answer this
Answered Forum FAQs
  • ARM Community
 0 votes 4566 views 0 replies Started 8 months ago by Annie Answer this
Not answered Unaligned transfer pattern in AXI4
  • Protocols
 0 votes 121 views 0 replies Started yesterday by Supal Answer this
Not answered AHB - continue the transfer after an error response 0 votes 272 views 0 replies Started yesterday by Joon Hong Answer this
Not answered Flash Patching in Cortex M7
  • Arm7
  • Cortex-M7
  • System architectures
 0 votes 364 views 0 replies Started 2 days ago by SaiGautamJP Answer this
Answered HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2) 0 votes 553 views 2 replies Latest 3 days ago by Tapas Answer this
Answered Forum FAQs Started 8 months ago by Annie 0 replies 5556 views
Answered Forum FAQs Started 8 months ago by Annie 0 replies 4566 views
Not answered Unaligned transfer pattern in AXI4 Started yesterday by Supal 0 replies 121 views
Not answered AHB - continue the transfer after an error response Started yesterday by Joon Hong 0 replies 272 views
Not answered Flash Patching in Cortex M7 Started 2 days ago by SaiGautamJP 0 replies 364 views
Answered HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2) Latest 3 days ago by Tapas 2 replies 553 views