CoreLink CCI-400

The Arm CoreLink CCI-400 Cache Coherent Interconnect

Premium Mobile CCI400 System Diagram.

Getting Started

The Arm CoreLink CCI-400 Cache Coherent Interconnect provides full cache coherency between two clusters of multi-core CPUs. It enables big.LITTLE processing and I/O coherency for devices such as the Mali-T600 series GPU, and I/O masters like modem and USB. First released in 2011, CoreLink CCI-400 has been widely licensed and is today shipping in many millions of production devices.

CoreLink CPE-425 Coherent PCIe Extension for CCI-400 Diagram

CoreLink CPE-425 Coherent PCIe Extension for CCI-400

The Arm CPE-425 Coherent PCIe Extension for Corelink CCI-400 is a companion product available through Flexible Access. A small overview of the extension:

  • A companion product for Corelink CCI-400
  • Enables IO Coherent PCIe for Corelink CCI-400
  • Allows CPU write backs to flow, removing known deadlocks and terminating barriers

Specifications

 Features Details
 AMBA Specifications
 AMBA 4 ACE and ACE-Lite
 ACE Slave interfaces 2 for fully coherent processors including Arm Cortex
 ACE-Lite slave interfaces 1-3 for IO coherent devices such as Mali processors, accelerators and IO
 Memory and System master interfaces

1-2 memory interfaces
1 system interface
 Coherency
 Broadcast snoop protocol
 Memory map 40 bit Physical, configurable address map
44 bit DVM

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

Learn more

  • TRM

  • CoreLink CCI-400 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    CCI-400 TRM
  • A guide on software optimization.

  • AMBA 4 ACE Specification

    CoreLink CCI-400 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs
  • A program that is running on a desktop.

  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.


    Learn more

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Community Forums

Not answered Porting to U-boot driver model and device tree control (for ARM-based design)
  • Peripheral Devices
  • U-Boot
 0 votes 181 views 0 replies Started yesterday by Rob Damico Answer this
Not answered httpd web server on stm32f407vg
  • STM32 F4
 0 votes 165 views 0 replies Started yesterday by rpj Answer this
Not answered AXI4 transaction attributes 0 votes 193 views 0 replies Started 5 days ago by Ravi V. Answer this
Suggested answer AMBA 5 CHI Link Layer (L-Credit Return)
  • AMBA 5 CHI
  • CHI
  • Cache Coherent Interconnect
  • AMBA 5
 0 votes 1785 views 3 replies Latest 6 days ago by Christopher Tory Answer this
Answered Is AXI4 Ordered write observation used to support PCIE Producer/Consumer ordering model?
  • AXI4
 0 votes 317 views 1 replies Latest 7 days ago by Christopher Tory Answer this
Suggested answer BUSY transfer just before the last transfer in a burst by a AHB Master. 0 votes 1308 views 1 replies Latest 22 days ago by Colin Campbell Answer this
Not answered Porting to U-boot driver model and device tree control (for ARM-based design) Started yesterday by Rob Damico 0 replies 181 views
Not answered httpd web server on stm32f407vg Started yesterday by rpj 0 replies 165 views
Not answered AXI4 transaction attributes Started 5 days ago by Ravi V. 0 replies 193 views
Suggested answer AMBA 5 CHI Link Layer (L-Credit Return) Latest 6 days ago by Christopher Tory 3 replies 1785 views
Answered Is AXI4 Ordered write observation used to support PCIE Producer/Consumer ordering model? Latest 7 days ago by Christopher Tory 1 replies 317 views
Suggested answer BUSY transfer just before the last transfer in a burst by a AHB Master. Latest 22 days ago by Colin Campbell 1 replies 1308 views