CoreLink CCI-400

The Arm CoreLink CCI-400 Cache Coherent Interconnect

Premium Mobile CCI400 System Diagram.

Getting Started

The Arm CoreLink CCI-400 Cache Coherent Interconnect provides full cache coherency between two clusters of multi-core CPUs. It enables big.LITTLE processing and I/O coherency for devices such as the Mali-T600 series GPU, and I/O masters like modem and USB. First released in 2011, CoreLink CCI-400 has been widely licensed and is today shipping in many millions of production devices.


CoreLink CPE-425 Coherent PCIe Extension for CCI-400 Diagram

CoreLink CPE-425 Coherent PCIe Extension for CCI-400

The Arm CPE-425 Coherent PCIe Extension for Corelink CCI-400 is a companion product available through Flexible Access. A small overview of the extension:

  • A companion product for Corelink CCI-400
  • Enables IO Coherent PCIe for Corelink CCI-400
  • Allows CPU write backs to flow, removing known deadlocks and terminating barriers

Specifications

 Features Details
 AMBA Specifications
AMBA 4 ACE and ACE-Lite
 ACE Slave interfaces 2 for fully coherent processors including Arm Cortex
 ACE-Lite slave interfaces 1-3 for IO coherent devices such as Mali processors, accelerators and IO
 Memory and System master interfaces

1-2 memory interfaces
1 system interface

 Coherency
Broadcast snoop protocol
 Memory map 40 bit Physical, configurable address map
44 bit DVM

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.


  • TRM
  • CoreLink CCI-400 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    CCI-400 TRM
  • A guide on software optimization.
  • AMBA 4 ACE Specification

    CoreLink CCI-400 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs
  • A program that is running on a desktop.
  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.


    Learn more

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Community Blogs

Community Forums

Not answered outsanading behaviour in AXI Vs memory latency
  • AMBA 4
  • AMBA 3 AXI Interface
0 votes 304 views 0 replies Started 2 days ago by vereng Answer this
Suggested answer ARM AMBA AXI4 read channel information
  • AXI4
0 votes 891 views 1 replies Latest 3 days ago by Colin Campbell Answer this
Suggested answer stm32h753 rtc resets after power down (vbat is connected)
  • STM32
0 votes 1128 views 1 replies Latest 3 days ago by Andy Neil Answer this
Suggested answer I2C problem on Cypress PSoC3 (with EEPROM and FRAM too) 0 votes 733 views 3 replies Latest 3 days ago by Andy Neil Answer this
Answered outstanding transaction in AXI4 protocol 0 votes 8201 views 4 replies Latest 6 days ago by Colin Campbell Answer this
Suggested answer Help with AXI4 payload with data bus width of 32 bits
  • AXI4
0 votes 1276 views 1 replies Latest 6 days ago by Colin Campbell Answer this
Not answered outsanading behaviour in AXI Vs memory latency Started 2 days ago by vereng 0 replies 304 views
Suggested answer ARM AMBA AXI4 read channel information Latest 3 days ago by Colin Campbell 1 replies 891 views
Suggested answer stm32h753 rtc resets after power down (vbat is connected) Latest 3 days ago by Andy Neil 1 replies 1128 views
Suggested answer I2C problem on Cypress PSoC3 (with EEPROM and FRAM too) Latest 3 days ago by Andy Neil 3 replies 733 views
Answered outstanding transaction in AXI4 protocol Latest 6 days ago by Colin Campbell 4 replies 8201 views
Suggested answer Help with AXI4 payload with data bus width of 32 bits Latest 6 days ago by Colin Campbell 1 replies 1276 views