CoreLink CCI-400

The Arm CoreLink CCI-400 Cache Coherent Interconnect

Premium Mobile CCI400 System Diagram.

Getting Started

The Arm CoreLink CCI-400 Cache Coherent Interconnect provides full cache coherency between two clusters of multi-core CPUs. It enables big.LITTLE processing and I/O coherency for devices such as the Mali-T600 series GPU, and I/O masters like modem and USB. First released in 2011, CoreLink CCI-400 has been widely licensed and is today shipping in many millions of production devices.


CoreLink CPE-425 Coherent PCIe Extension for CCI-400

The Arm CPE-425 Coherent PCIe Extension for Corelink CCI-400 is a companion product available through Flexible Access. A small overview of the extension:

  • A companion product for Corelink CCI-400
  • Enables IO Coherent PCIe for Corelink CCI-400
  • Allows CPU write backs to flow, removing known deadlocks and terminating barriers

Specifications

 Features Details
 AMBA Specifications
AMBA 4 ACE and ACE-Lite
 ACE Slave interfaces 2 for fully coherent processors including Arm Cortex
 ACE-Lite slave interfaces 1-3 for IO coherent devices such as Mali processors, accelerators and IO
 Memory and System master interfaces

1-2 memory interfaces
1 system interface

 Coherency
Broadcast snoop protocol
 Memory map 40 bit Physical, configurable address map
44 bit DVM

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.


  • TRM
  • CoreLink CCI-400 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    CCI-400 TRM
  • A guide on software optimization.
  • AMBA 4 ACE Specification

    CoreLink CCI-400 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs
  • A program that is running on a desktop.
  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.


    Learn more

Get support

Community Forums

Answered Forum FAQs
  • ARM Community
0 votes 3361 views 0 replies Started 4 months ago by Annie Answer this
Answered Forum FAQs
  • ARM Community
0 votes 3269 views 0 replies Started 4 months ago by Annie Answer this
Not answered 2-D Convolution with CMSIS
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0 votes 29 views 0 replies Started 9 hours ago by icebeing Answer this
Not answered How to determine HREADY during master change the selected slave? 0 votes 25 views 0 replies Started 12 hours ago by jack5566 Answer this
Suggested answer Cortex M4 hard fault finding root cause on LPC4078 pc=0x0
  • R15 (PC Program Counter)
  • 3 (HardFault)
0 votes 1771 views 15 replies Latest 3 days ago by tobermory Answer this
Suggested answer ARM Cortex ICode, DCode, System buses
  • APB
  • AMBA
  • SRAM
  • Cortex-M3
  • Bus Architecture
  • Cortex-M
  • Memory
0 votes 15500 views 9 replies Latest 8 days ago by ele Answer this
Answered Forum FAQs Started 4 months ago by Annie 0 replies 3361 views
Answered Forum FAQs Started 4 months ago by Annie 0 replies 3269 views
Not answered 2-D Convolution with CMSIS Started 9 hours ago by icebeing 0 replies 29 views
Not answered How to determine HREADY during master change the selected slave? Started 12 hours ago by jack5566 0 replies 25 views
Suggested answer Cortex M4 hard fault finding root cause on LPC4078 pc=0x0 Latest 3 days ago by tobermory 15 replies 1771 views
Suggested answer ARM Cortex ICode, DCode, System buses Latest 8 days ago by ele 9 replies 15500 views