CoreLink CCI-500

The Arm CoreLink CCI-500 Cache Coherent Interconnect

Getting Started

The Arm CoreLink CCI-500 Cache Coherent Interconnect extends the performance and low power leadership of Arm mobile systems. It provides full cache coherency between big.LITTLE processor clusters and provides I/O coherency for other agents such as Mali GPU, network interfaces or accelerators. CoreLink CCI-500 offers a scalable and configurable interconnect which enables SoC designers to meet the performance goals with the smallest possible area and power.

Specifications

 Features Details
 AMBA AMBA 4 ACE and ACE-Lite
 ACE slave interfaces 1-4 for fully coherent processors including Arm Cortex
 ACE-Lite slave interfaces 0-6 for IO coherent devices such as Mali processors, accelerators and IO such as PCIe root complex
 Memory and System master interfaces 1-4 memory interfaces
1-2 system interfaces
 Coherency and snoop filter Integrated snoop filter maintains directory of 
processor cache contents, reduces CPU snoops and reduces system power
 Memory map 32-48 bit physical address width, configurable address map
40, 44, or 48-bit DVM

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

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  • TRM

  • CoreLink CCI-500 TRM

    For system designers, system integrators and programmers who are designing a SoC, the TRM is the go-to resource.

    CCI-500 TRM
  • A guide on software optimization.

  • AMBA 4 ACE Specification

    CoreLink CCI-500 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency designs.

    AMBA specs
  • A program that is running on a desktop.

  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.

    Learn more
  • A program that is running on a desktop.

  • System Validation at Arm

    Enabling Partners to Build Better Systems

    Download
  • A program that is running on a desktop.

  • Introduction to AMBA 4 ACE

    Focused on AMBA ACE and ACE-Lite interfaces, which introduce system-level coherency, cache maintenance, Distributed Virtual Memory (DVM) and barrier transaction support. It enables big.LITTLE software to run effectively, increasing system efficiency.

    Download
  • A program that is running on a desktop.

  • Quality of Service in Arm Systems

    Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in Arm systems.

    Download
  • A program that is running on a desktop.

  • QoS for Performant and Efficient HD Media.

    Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

    Download

Introduction Video

Learn more about CoreLink CCI-500 features, applications and benefits.

Watch video

Get support

Community Blogs

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Simplifying workload modeling with AMBA ATP Engine

Following the release of the AMBA Adaptive Traffic Profiles (ATP) Specification, we are pleased to announce the AMBA ATP Engine, to further facilitate ATP’s adoption into a variety of platforms.

2 months ago by Francisco Socal
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3 months ago by Jason Andrews
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Arm is proud to announce the addition of Arm Safety Packages for select IP within Arm Flexible Access, with the goal to make it easier for developers in the automotive and other safety-related industries to create SoCs.

5 months ago by Chet Babla
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Functional Safety on Arm – Beyond Automotive

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7 months ago by Antonio Priore
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Docker enables Arm Cycle Model Studio on Ubuntu

Arm Cycle Model Studio (CMS) is a great tool to create SystemC simulation models from Verilog RTL source code. This articles shows how to use Docker to run CMS and create models on an Ubuntu machine.

9 months ago by Jason Andrews
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Community Forums

Answered which kind of code is calling the microlib of __aeabi_uread4(uread4)
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Answered STM32F411RE: cannot use #include math_arm.h for CMSIS
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  • Digital Signal Processor (DSP)
  • CMSIS
 1 votes 25232 views 7 replies Latest 8 days ago by HonestTrooper Answer this
Answered which kind of code is calling the microlib of __aeabi_uread4(uread4) Latest 20 hours ago by Wei Jetim. Zhao 2 replies 220 views
Answered Implementing a non-hanging USB listener Latest 2 days ago by Kev 30 replies 2339 views
Answered Why does the printf debug only print weird symbols? Latest 5 days ago by coldspark 16 replies 1117 views
Answered lpc1768 no USB Host component? Latest 7 days ago by Kev 3 replies 299 views
Answered Cannot access memory of LPC1769 Latest 7 days ago by coldspark 1 replies 228 views
Answered STM32F411RE: cannot use #include math_arm.h for CMSIS Latest 8 days ago by HonestTrooper 7 replies 25232 views