CoreLink CCI-500

The Arm CoreLink CCI-500 Cache Coherent Interconnect

Getting Started

The Arm CoreLink CCI-500 Cache Coherent Interconnect extends the performance and low power leadership of Arm mobile systems. It provides full cache coherency between big.LITTLE processor clusters and provides I/O coherency for other agents such as Mali GPU, network interfaces or accelerators. CoreLink CCI-500 offers a scalable and configurable interconnect which enables SoC designers to meet the performance goals with the smallest possible area and power.

Specifications

 Features Details
 AMBA AMBA 4 ACE and ACE-Lite
 ACE slave interfaces 1-4 for fully coherent processors including Arm Cortex
 ACE-Lite slave interfaces 0-6 for IO coherent devices such as Mali processors, accelerators and IO such as PCIe root complex
 Memory and System master interfaces 1-4 memory interfaces
1-2 system interfaces
 Coherency and snoop filter Integrated snoop filter maintains directory of 
processor cache contents, reduces CPU snoops and reduces system power
 Memory map 32-48 bit physical address width, configurable address map
40, 44, or 48-bit DVM

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Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

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  • TRM

  • CoreLink CCI-500 TRM

    For system designers, system integrators and programmers who are designing a SoC, the TRM is the go-to resource.

    CCI-500 TRM
  • A guide on software optimization.

  • AMBA 4 ACE Specification

    CoreLink CCI-500 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency designs.

    AMBA specs
  • A program that is running on a desktop.

  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.

    Learn more
  • A program that is running on a desktop.

  • System Validation at Arm

    Enabling Partners to Build Better Systems

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  • A program that is running on a desktop.

  • Introduction to AMBA 4 ACE

    Focused on AMBA ACE and ACE-Lite interfaces, which introduce system-level coherency, cache maintenance, Distributed Virtual Memory (DVM) and barrier transaction support. It enables big.LITTLE software to run effectively, increasing system efficiency.

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  • A program that is running on a desktop.

  • Quality of Service in Arm Systems

    Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in Arm systems.

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  • A program that is running on a desktop.

  • QoS for Performant and Efficient HD Media.

    Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

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Introduction Video

Learn more about CoreLink CCI-500 features, applications and benefits.

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Answered How to disable Misra C single item in PCLint Latest 2 days ago by Robert Rostohar 1 replies 156 views
Answered Fota application on stm32f4 Latest 2 days ago by ein 2 replies 624 views
Answered Disassembly differences Latest 3 days ago by ludw 8 replies 1012 views
Answered Keil MDK5 HTTP server - form input names Latest 6 days ago by Murilo Machado 3 replies 807 views
Answered Reset process in microcontrollers Latest 8 days ago by Andy Neil 1 replies 272 views
Answered Link a pure binary file to image with scatter file Latest 9 days ago by Ronan Synnott 3 replies 1952 views