CoreLink CCI-500

The Arm CoreLink CCI-500 Cache Coherent Interconnect

Getting Started

The Arm CoreLink CCI-500 Cache Coherent Interconnect extends the performance and low power leadership of Arm mobile systems. It provides full cache coherency between big.LITTLE processor clusters and provides I/O coherency for other agents such as Mali GPU, network interfaces or accelerators. CoreLink CCI-500 offers a scalable and configurable interconnect which enables SoC designers to meet the performance goals with the smallest possible area and power.


Specifications

 Features Details
 AMBA AMBA 4 ACE and ACE-Lite
 ACE slave interfaces 1-4 for fully coherent processors including Arm Cortex
 ACE-Lite slave interfaces 0-6 for IO coherent devices such as Mali processors, accelerators and IO such as PCIe root complex
 Memory and System master interfaces 1-4 memory interfaces
1-2 system interfaces
 Coherency and snoop filter Integrated snoop filter maintains directory of 
processor cache contents, reduces CPU snoops and reduces system power
 Memory map 32-48 bit physical address width, configurable address map
40, 44, or 48-bit DVM

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.


  • TRM
  • CoreLink CCI-500 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    CCI-500 TRM
  • A guide on software optimization.
  • AMBA 4 ACE Specification

    CoreLink CCI-500 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency designs.

    AMBA specs
  • A program that is running on a desktop.
  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.

    Learn more
  • A program that is running on a desktop.
  • System Validation at Arm

    Enabling Partners to Build Better Systems

    Download
  • A program that is running on a desktop.
  • Introduction to AMBA 4 ACE

    This paper focuses on the AMBA ACE and ACE-Lite interfaces, which introduce system-level coherency, cache maintenance, Distributed Virtual Memory (DVM) and barrier transaction support. It is used for multi-core processor systems to enable big.LITTLE software to run effectively, increasing system efficiency.

    Download
  • A program that is running on a desktop.
  • Quality of Service (QoS) in Arm Systems: An Overview

    Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in Arm systems.

    Download
  • A program that is running on a desktop.
  • QoS for High-Performance and Power-Efficient HD Media... - Arm

    Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

    Download

Introduction Video

Learn more about CoreLink CCI-500 features, applications and benefits.

Watch video


Get support

Useful whitepapers

System Validation at Arm: Enabling Partners to Build Better Systems

Introduction to AMBA 4 ACE

This paper focuses on the AMBA ACE and ACE-Lite interfaces, which introduce system-level coherency, cache maintenance, Distributed Virtual Memory (DVM) and barrier transaction support. It is used for multi-core processor systems to enable big.LITTLE software to run effectively, increasing system efficiency. 

Quality of Service (QoS) in Arm Systems: An Overview

Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in Arm systems. 

QoS for High-Performance and Power-Efficient HD Media... - Arm

Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

Introduction to QoS Virtual Networks (QVN)

This white paper explains a new mechanism for reducing the congestion in systems via QoS Virtual Networks. QVN makes system latency and bandwidth deterministic and predictable; preventing blocking in the interconnect by ensuring that a transaction can be accepted before it’s initiated.


Community Blogs

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Answered UART Baud rate CMSIS Drivers 0 votes 1543 views 6 replies Latest 3 days ago by Robert McNamara Answer this
Answered DSTREAM networking ports 0 votes 464 views 3 replies Latest 4 days ago by Stephen Theobald Answer this
Answered DSTREAM network configuration from linux 0 votes 449 views 2 replies Latest 5 days ago by Joe Kulig Answer this
Answered STM32F411RE: cannot use #include math_arm.h for CMSIS
  • STM32F4DISCOVERY
  • Digital Signal Processor (DSP)
  • CMSIS
1 votes 11594 views 6 replies Latest 5 days ago by Andy Neil Answer this
Answered Two different functions but with the same name in separate libraries 0 votes 2665 views 12 replies Latest 5 days ago by Andy Neil Answer this
Answered Facing Debugging Code size limitation. 0 votes 761 views 4 replies Latest 6 days ago by Tripathi Dharmesh Answer this
Answered UART Baud rate CMSIS Drivers Latest 3 days ago by Robert McNamara 6 replies 1543 views
Answered DSTREAM networking ports Latest 4 days ago by Stephen Theobald 3 replies 464 views
Answered DSTREAM network configuration from linux Latest 5 days ago by Joe Kulig 2 replies 449 views
Answered STM32F411RE: cannot use #include math_arm.h for CMSIS Latest 5 days ago by Andy Neil 6 replies 11594 views
Answered Two different functions but with the same name in separate libraries Latest 5 days ago by Andy Neil 12 replies 2665 views
Answered Facing Debugging Code size limitation. Latest 6 days ago by Tripathi Dharmesh 4 replies 761 views