CoreLink CCI-550

The Arm CoreLink CCI-550 Cache Coherent Interconnect

Getting Started

The Arm CoreLink CCI-550 Cache Coherent Interconnect expands on the successful CoreLink CCI-500.  It provides full cache coherency between big.LITTLE processor clusters and provides I/O coherency for other agents such as Mali GPU, network interfaces or accelerators. CoreLink CCI-550 offers a scalable and configurable interconnect which enables SoC designers to meet the performance goals with the smallest possible area and power and also adds a snoop filter which lowers overall system latency.

Specifications

 Features Details
 AMBA AMBA 4 ACE
 ACE Slave interfaces 1-6 for fully coherent processors including Arm Cortex and Mali GPU
 Memory and System master interfaces 1-6 memory interfaces
1-3 system interfaces
 Coherency and snoop filter Integrated snoop filter maintains directory of 
processor cache contents, reduces CPU snoops and reduces system power
 Memory map 32-48 bit physical address width, configurable address map
40, 44, or 48-bit DVM

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

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  • TRM

  • CoreLink CCI-550 TRM

    For system designers, system integrators and programmers who are designing a SoC, the TRMl is the go-to resource.

    CCI-550 TRM
  • A guide on software optimization.

  • AMBA 4 ACE Specification

    CoreLink CCI-550 is built on the AMBA 4 ACE specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs
  • A program that is running on a desktop.

  • Quality of Service (QoS) in Arm Systems

    Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in Arm systems.

    Download
  • A program that is running on a desktop.

  • QoS for Performant and Efficient HD Media.

    Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

    Download
  • A program that is running on a desktop.

  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.

    Learn more

Get support

Community Blogs

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Simplifying workload modeling with AMBA ATP Engine

Following the release of the AMBA Adaptive Traffic Profiles (ATP) Specification, we are pleased to announce the AMBA ATP Engine, to further facilitate ATP’s adoption into a variety of platforms.

1 months ago by Francisco Socal
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1 months ago by Jason Andrews
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4 months ago by Chet Babla
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6 months ago by Antonio Priore
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Docker enables Arm Cycle Model Studio on Ubuntu

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8 months ago by Jason Andrews
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Community Forums

Answered ARM vs Thumb vs Thumb2 instruction set
  • T32 (Thumb)
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Answered ARM/THUMB instructions that change execution path?
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Not answered ACE-Lite 0 votes 17 views 0 replies Started yesterday by Ishan Answer this
Not answered Porting to U-boot driver model and device tree control (for ARM-based design)
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Not answered AXI4 transaction attributes 0 votes 195 views 0 replies Started 6 days ago by Ravi V. Answer this
Answered ARM vs Thumb vs Thumb2 instruction set Latest 12 hours ago by Kevin B 2 replies 8520 views
Answered ARM/THUMB instructions that change execution path? Latest yesterday by jakebunt 77 replies 61148 views
Not answered ACE-Lite Started yesterday by Ishan 0 replies 17 views
Not answered Porting to U-boot driver model and device tree control (for ARM-based design) Started 2 days ago by Rob Damico 0 replies 188 views
Not answered httpd web server on stm32f407vg Started 2 days ago by rpj 0 replies 170 views
Not answered AXI4 transaction attributes Started 6 days ago by Ravi V. 0 replies 195 views