CoreLink CCI-550

The Arm CoreLink CCI-550 Cache Coherent Interconnect

Getting Started

The Arm CoreLink CCI-550 Cache Coherent Interconnect provides full cache coherency between big.LITTLE processor clusters, Mali GPU, and other agents such as network interfaces or accelerators. It can support up to six ACE interfaces and six memory interfaces for the efficient movement of data across the SoC.

CCI-550 provides:

  • A trusted interconnect solution enabling multiple applications.

  • Optimized path to memory that enhances the user experience.

  • Highest efficiency coherent interconnect.


Specifications

 Features Details
 AMBA AMBA 4 ACE
 ACE Slave interfaces 1-6 for fully coherent processors including Arm Cortex and Mali GPU
 Memory and System master interfaces 1-6 memory interfaces
1-3 system interfaces
 Coherency and snoop filter Integrated snoop filter maintains directory of 
processor cache contents, reduces CPU snoops and reduces system power
 Memory map 32-48 bit physical address width, configurable address map
40, 44, or 48-bit DVM

  • TRM
  • CoreLink CCI-550 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    CCI-550 TRM
  • A guide on software optimization.
  • AMBA 4 ACE Specification

    CoreLink CCI-550 is built on the AMBA 4 ACE specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs
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  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.

    Learn more
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  • System Validation at Arm

    Enabling Partners to Build Better Systems

    Download
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  • Introduction to AMBA 4 ACE

    This paper focuses on the AMBA ACE and ACE-Lite interfaces, which introduce system-level coherency, cache maintenance, Distributed Virtual Memory (DVM) and barrier transaction support. It is used for multi-core processor systems to enable big.LITTLE software to run effectively, increasing system efficiency.

    Download
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  • Quality of Service (QoS) in Arm Systems: An Overview

    Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in Arm systems.

    Download
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  • QoS for High-Performance and Power-Efficient HD Media... - Arm

    Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

    Download

Resources

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Not answered Aligned and unaligned word transfers on a 64-bit bus
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0 votes 247 views 0 replies Started 3 days ago by Maria_d Answer this
Suggested answer CMSIS: Storage interface vs Flash interface - what's the difference ?
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Suggested answer What SBCs I need to choose?
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0 votes 438 views 1 replies Latest 5 days ago by Andy Neil Answer this
Not answered Does anyone knows why a documentation as ARM DSU 0030 is only available for licensees 0 votes 380 views 0 replies Started 5 days ago by JaWa Answer this
Suggested answer The meanings of AxCACHE 0 votes 431 views 1 replies Latest 8 days ago by Christopher Tory Answer this
Suggested answer CoreLink NIC-400 Interconnect gives an extra request
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0 votes 503 views 1 replies Latest 8 days ago by Christopher Tory Answer this
Not answered Aligned and unaligned word transfers on a 64-bit bus Started 3 days ago by Maria_d 0 replies 247 views
Suggested answer CMSIS: Storage interface vs Flash interface - what's the difference ? Latest 4 days ago by Vladimir Umek 1 replies 456 views
Suggested answer What SBCs I need to choose? Latest 5 days ago by Andy Neil 1 replies 438 views
Not answered Does anyone knows why a documentation as ARM DSU 0030 is only available for licensees Started 5 days ago by JaWa 0 replies 380 views
Suggested answer The meanings of AxCACHE Latest 8 days ago by Christopher Tory 1 replies 431 views
Suggested answer CoreLink NIC-400 Interconnect gives an extra request Latest 8 days ago by Christopher Tory 1 replies 503 views