CoreLink CCI-550

The Arm CoreLink CCI-550 Cache Coherent Interconnect

Getting Started

The Arm CoreLink CCI-550 Cache Coherent Interconnect expands on the successful CoreLink CCI-500.  It provides full cache coherency between big.LITTLE processor clusters and provides I/O coherency for other agents such as Mali GPU, network interfaces or accelerators. CoreLink CCI-550 offers a scalable and configurable interconnect which enables SoC designers to meet the performance goals with the smallest possible area and power and also adds a snoop filter which lowers overall system latency.

Specifications

 Features Details
 AMBA AMBA 4 ACE
 ACE Slave interfaces 1-6 for fully coherent processors including Arm Cortex and Mali GPU
 Memory and System master interfaces 1-6 memory interfaces
1-3 system interfaces
 Coherency and snoop filter Integrated snoop filter maintains directory of 
processor cache contents, reduces CPU snoops and reduces system power
 Memory map 32-48 bit physical address width, configurable address map
40, 44, or 48-bit DVM

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  • TRM

  • CoreLink CCI-550 TRM

    For system designers, system integrators and programmers who are designing a SoC, the TRMl is the go-to resource.

    CCI-550 TRM
  • A guide on software optimization.

  • AMBA 4 ACE Specification

    CoreLink CCI-550 is built on the AMBA 4 ACE specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs
  • A program that is running on a desktop.

  • Quality of Service (QoS) in Arm Systems

    Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in Arm systems.

    Download
  • A program that is running on a desktop.

  • QoS for Performant and Efficient HD Media.

    Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

    Download
  • A program that is running on a desktop.

  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.

    Learn more

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Answered Forum FAQs
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 0 votes 4557 views 0 replies Started 8 months ago by Annie Answer this
Answered HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2) 0 votes 128 views 2 replies Latest 16 hours ago by Tapas Answer this
Not answered A power electronics controls in C/C++ embedded and software pointer for PC program
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Suggested answer How to calculate AXI interleave depth and reorder depth.
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Answered One master to two slave transfer (back to back) behavior for address A (slave1) and address B (slave2) 0 votes 226 views 1 replies Latest 4 days ago by Colin Campbell Answer this
Answered Forum FAQs Started 8 months ago by Annie 0 replies 5202 views
Answered Forum FAQs Started 8 months ago by Annie 0 replies 4557 views
Answered HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2) Latest 16 hours ago by Tapas 2 replies 128 views
Not answered A power electronics controls in C/C++ embedded and software pointer for PC program Started yesterday by Md Mubdiul 0 replies 40 views
Suggested answer How to calculate AXI interleave depth and reorder depth. Latest 3 days ago by Koalassy 3 replies 3757 views
Answered One master to two slave transfer (back to back) behavior for address A (slave1) and address B (slave2) Latest 4 days ago by Colin Campbell 1 replies 226 views