CoreLink CCI-550

The Arm CoreLink CCI-550 Cache Coherent Interconnect

Getting Started

The Arm CoreLink CCI-550 Cache Coherent Interconnect expands on the successful CoreLink CCI-500.  It provides full cache coherency between big.LITTLE processor clusters and provides I/O coherency for other agents such as Mali GPU, network interfaces or accelerators. CoreLink CCI-550 offers a scalable and configurable interconnect which enables SoC designers to meet the performance goals with the smallest possible area and power and also adds a snoop filter which lowers overall system latency.


Specifications

 Features Details
 AMBA AMBA 4 ACE
 ACE Slave interfaces 1-6 for fully coherent processors including Arm Cortex and Mali GPU
 Memory and System master interfaces 1-6 memory interfaces
1-3 system interfaces
 Coherency and snoop filter Integrated snoop filter maintains directory of 
processor cache contents, reduces CPU snoops and reduces system power
 Memory map 32-48 bit physical address width, configurable address map
40, 44, or 48-bit DVM

Start designing now

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  • TRM
  • CoreLink CCI-550 TRM

    For system designers, system integrators and programmers who are designing a SoC, the TRMl is the go-to resource.

    CCI-550 TRM
  • A guide on software optimization.
  • AMBA 4 ACE Specification

    CoreLink CCI-550 is built on the AMBA 4 ACE specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs
  • A program that is running on a desktop.
  • Quality of Service (QoS) in Arm Systems

    Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in Arm systems.

    Download
  • A program that is running on a desktop.
  • QoS for Performant and Efficient HD Media.

    Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

    Download
  • A program that is running on a desktop.
  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.

    Learn more

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Community Blogs

Community Forums

Not answered In APB, Why do we use enable signal? (Don't care about PREADY) 0 votes 30 views 0 replies Started 20 hours ago by INNS Answer this
Suggested answer DC/DC Controller SoC 0 votes 475 views 1 replies Latest 4 days ago by Andy Neil Answer this
Suggested answer AMBA 5 CHI : Does Interleaving of TxnID within a Multiple flits message allowed?
  • System on Chip (SoC)
  • AMBA 5 CHI
  • CHI
  • Cache Architecture
0 votes 610 views 1 replies Latest 7 days ago by IPDeveloper Answer this
Answered ARM vs Thumb vs Thumb2 instruction set
  • T32 (Thumb)
0 votes 9104 views 2 replies Latest 9 days ago by Kevin B Answer this
Answered ARM/THUMB instructions that change execution path?
  • Thumb
0 votes 62003 views 77 replies Latest 9 days ago by jakebunt Answer this
Not answered ACE-Lite 0 votes 412 views 0 replies Started 9 days ago by Ishan Answer this
Not answered In APB, Why do we use enable signal? (Don't care about PREADY) Started 20 hours ago by INNS 0 replies 30 views
Suggested answer DC/DC Controller SoC Latest 4 days ago by Andy Neil 1 replies 475 views
Suggested answer AMBA 5 CHI : Does Interleaving of TxnID within a Multiple flits message allowed? Latest 7 days ago by IPDeveloper 1 replies 610 views
Answered ARM vs Thumb vs Thumb2 instruction set Latest 9 days ago by Kevin B 2 replies 9104 views
Answered ARM/THUMB instructions that change execution path? Latest 9 days ago by jakebunt 77 replies 62003 views
Not answered ACE-Lite Started 9 days ago by Ishan 0 replies 412 views