CoreLink CCI-550

The Arm CoreLink CCI-550 Cache Coherent Interconnect

Getting Started

The Arm CoreLink CCI-500 Cache Coherent Interconnect extends the performance and low power leadership of Arm mobile systems. It provides full cache coherency between big.LITTLE processor clusters and provides I/O coherency for other agents such as Mali GPU, network interfaces or accelerators. CoreLink CCI-500 offers a scalable and configurable interconnect which enables SoC designers to meet the performance goals with the smallest possible area and power.

Specifications

 Features Details
 AMBA AMBA 4 ACE
 ACE Slave interfaces 1-6 for fully coherent processors including Arm Cortex and Mali GPU
 Memory and System master interfaces 1-6 memory interfaces
1-3 system interfaces
 Coherency and snoop filter Integrated snoop filter maintains directory of 
processor cache contents, reduces CPU snoops and reduces system power
 Memory map 32-48 bit physical address width, configurable address map
40, 44, or 48-bit DVM

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

Learn more

  • TRM

  • CoreLink CCI-550 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    CCI-550 TRM
  • A guide on software optimization.

  • AMBA 4 ACE Specification

    CoreLink CCI-550 is built on the AMBA 4 ACE specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs
  • A program that is running on a desktop.

  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.

    Learn more
  • A program that is running on a desktop.

  • Quality of Service (QoS) in Arm Systems: An Overview

    Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in Arm systems.

    Download
  • A program that is running on a desktop.

  • QoS for High-Performance and Power-Efficient HD Media... - Arm

    Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

    Download

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Community Blogs

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Functional Safety on Arm – Beyond Automotive

Arm has moved a long way from the days where our only ‘safety’ requirement was to provide ECC or parity protections on CPU RAMs and we are now able to offer a number of System IP, GPUs, ISPs and NPUs as Safety Ready products. With Arm’s extensive…

1 months ago by Antonio Priore
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Docker enables Arm Cycle Model Studio on Ubuntu

Arm Cycle Model Studio (CMS) is a great tool to create SystemC simulation models from Verilog RTL source code. This articles shows how to use Docker to run CMS and create models on an Ubuntu machine.

3 months ago by Jason Andrews
2
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4 months ago by Andy Moore
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Unlocking Cortex-A53's Safety Potential

Arm will be introducing a Software Test Library (STL) on the Cortex-A53 processor. This is the first applications processor to have self-test Library software provided by Arm.

5 months ago by James Scobie
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AMBA ATP: Gaining momentum with workload modeling

This blog presents examples of AMBA ATP adoption and the benefits that Arm and its ecosystem partners deliver.

5 months ago by Francisco Socal
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Introducing Arm’s Functional Safety Partnership Program

Arm is proud to announce the launch of its Functional Safety Partnership Program which brings together partners in Arm’s broad ecosystem who specialize in the area of functional safety.

5 months ago by Antonio Priore

Community Forums

Not answered CHI protocol cache line states
  • AMBA 5 CHI
  • SoC Verification
 0 votes 685 views 0 replies Started 7 days ago by S_Seth Answer this
Not answered STM32F769i-Discovery IP Camera Interface 0 votes 801 views 0 replies Started 7 days ago by Kiran bhat Answer this
Suggested answer Store operations where the cache line is already cached (ACE protocol)
  • AMBA
  • AMBA 4
  • AXI
  • Interface
 2 votes 6989 views 9 replies Latest 8 days ago by het Answer this
Not answered Best most recent text on ARM arch 0 votes 640 views 0 replies Started 11 days ago by d.ry Answer this
Not answered Readunique and cleanunique transactions in ACE protocol
  • AMBA
  • AMBA 4
  • AXI4
 0 votes 796 views 0 replies Started 11 days ago by het Answer this
Suggested answer Raspberry pi 3 and .net 5 coreclr 1 votes 2741 views 2 replies Latest 11 days ago by delinaty Answer this
Not answered CHI protocol cache line states Started 7 days ago by S_Seth 0 replies 685 views
Not answered STM32F769i-Discovery IP Camera Interface Started 7 days ago by Kiran bhat 0 replies 801 views
Suggested answer Store operations where the cache line is already cached (ACE protocol) Latest 8 days ago by het 9 replies 6989 views
Not answered Best most recent text on ARM arch Started 11 days ago by d.ry 0 replies 640 views
Not answered Readunique and cleanunique transactions in ACE protocol Started 11 days ago by het 0 replies 796 views
Suggested answer Raspberry pi 3 and .net 5 coreclr Latest 11 days ago by delinaty 2 replies 2741 views