CoreLink CCI-550

The Arm CoreLink CCI-550 Cache Coherent Interconnect

Getting Started

The Arm CoreLink CCI-500 Cache Coherent Interconnect extends the performance and low power leadership of Arm mobile systems. It provides full cache coherency between big.LITTLE processor clusters and provides I/O coherency for other agents such as Mali GPU, network interfaces or accelerators. CoreLink CCI-500 offers a scalable and configurable interconnect which enables SoC designers to meet the performance goals with the smallest possible area and power.


Specifications

 Features Details
 AMBA AMBA 4 ACE
 ACE Slave interfaces 1-6 for fully coherent processors including Arm Cortex and Mali GPU
 Memory and System master interfaces 1-6 memory interfaces
1-3 system interfaces
 Coherency and snoop filter Integrated snoop filter maintains directory of 
processor cache contents, reduces CPU snoops and reduces system power
 Memory map 32-48 bit physical address width, configurable address map
40, 44, or 48-bit DVM

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

  • TRM
  • CoreLink CCI-550 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    CCI-550 TRM
  • A guide on software optimization.
  • AMBA 4 ACE Specification

    CoreLink CCI-550 is built on the AMBA 4 ACE specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs
  • A program that is running on a desktop.
  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.

    Learn more
  • A program that is running on a desktop.
  • Quality of Service (QoS) in Arm Systems: An Overview

    Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in Arm systems.

    Download
  • A program that is running on a desktop.
  • QoS for High-Performance and Power-Efficient HD Media... - Arm

    Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

    Download

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Not answered How to get Interrupt number (IRQ number) during kernel panic in interrupt context?
  • CoreLink GIC-400 Generic Interrupt Controller
  • Interrupt Handling
0 votes 351 views 0 replies Started 4 days ago by Rajeshkumar Answer this
Not answered Running .elf file on zynq board ubuntu platform Started 22 hours ago by dolly1192 0 replies 45 views
Not answered WID not present in AXI4 Started 3 days ago by Ravi V. 0 replies 124 views
Not answered Vacuum pump waste gas treatment equipment Started 4 days ago by lay1014 0 replies 184 views
Answered arm9 family nuvoton Latest 4 days ago by sridhar6994 1 replies 738 views
Answered NUVOTON N9H Latest 4 days ago by sridhar6994 6 replies 1520 views
Not answered How to get Interrupt number (IRQ number) during kernel panic in interrupt context? Started 4 days ago by Rajeshkumar 0 replies 351 views