CoreLink CCI-550

The Arm CoreLink CCI-550 Cache Coherent Interconnect

Getting Started

The Arm CoreLink CCI-550 Cache Coherent Interconnect expands on the successful CoreLink CCI-500.  It provides full cache coherency between big.LITTLE processor clusters and provides I/O coherency for other agents such as Mali GPU, network interfaces or accelerators. CoreLink CCI-550 offers a scalable and configurable interconnect which enables SoC designers to meet the performance goals with the smallest possible area and power and also adds a snoop filter which lowers overall system latency.

Specifications

 Features Details
 AMBA AMBA 4 ACE
 ACE Slave interfaces 1-6 for fully coherent processors including Arm Cortex and Mali GPU
 Memory and System master interfaces 1-6 memory interfaces
1-3 system interfaces
 Coherency and snoop filter Integrated snoop filter maintains directory of 
processor cache contents, reduces CPU snoops and reduces system power
 Memory map 32-48 bit physical address width, configurable address map
40, 44, or 48-bit DVM

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  • TRM

  • CoreLink CCI-550 TRM

    For system designers, system integrators and programmers who are designing a SoC, the TRMl is the go-to resource.

    CCI-550 TRM
  • A guide on software optimization.

  • AMBA 4 ACE Specification

    CoreLink CCI-550 is built on the AMBA 4 ACE specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs
  • A program that is running on a desktop.

  • Quality of Service (QoS) in Arm Systems

    Nearly all performance-oriented SoCs are dependent on high bandwidth and low latency external memory systems to deliver within cost and performance constraints. This paper goes through the QoS functions that help deliver predictable performance in Arm systems.

    Download
  • A program that is running on a desktop.

  • QoS for Performant and Efficient HD Media.

    Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

    Download
  • A program that is running on a desktop.

  • Extended System Coherency

    A three-part series of blogs on cache coherency fundamentals, and why they matter to system design.

    Learn more

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Community Forums

Answered Forum FAQs
  • ARM Community
 0 votes 2819 views 0 replies Started 1 months ago by Annie Cracknell Answer this
Answered Forum FAQs
  • ARM Community
 0 votes 2835 views 0 replies Started 1 months ago by Annie Cracknell Answer this
Not answered Does it use a Slow Clock to turn off Main Clock? 0 votes 32 views 0 replies Started yesterday by Ridge Mao Answer this
Answered Can re-order depth affect functionality of write transaction? 0 votes 507 views 5 replies Latest 2 days ago by Colin Campbell Answer this
Suggested answer Alignment Address Calculation in AHB
  • AMBA
  • AHB
  • Interface
 0 votes 11157 views 5 replies Latest 4 days ago by Colin Campbell Answer this
Suggested answer HTRANS when HREADY is low on the 2nd HCLK after starting the transfer
  • AMBA 3 AHB Interface
  • AHB
 0 votes 262 views 1 replies Latest 4 days ago by Colin Campbell Answer this
Answered Forum FAQs Started 1 months ago by Annie Cracknell 0 replies 2819 views
Answered Forum FAQs Started 1 months ago by Annie Cracknell 0 replies 2835 views
Not answered Does it use a Slow Clock to turn off Main Clock? Started yesterday by Ridge Mao 0 replies 32 views
Answered Can re-order depth affect functionality of write transaction? Latest 2 days ago by Colin Campbell 5 replies 507 views
Suggested answer Alignment Address Calculation in AHB Latest 4 days ago by Colin Campbell 5 replies 11157 views
Suggested answer HTRANS when HREADY is low on the 2nd HCLK after starting the transfer Latest 4 days ago by Colin Campbell 1 replies 262 views