Specifications

CoreLink CI-700 is a configurable and scalable coherent interconnect that is designed with Armv9 processors to provide a Total Compute solution. Designed, verified, and performance and power optimized with other Arm IP as part of a solution focused on the latest premium mobile use cases. It is scalable from mainstream to premium smartphones all the way up to laptop class devices. Designed to be paired with CoreLink Network Interconnect and CoreLink MMU-700 Memory Management Unit.

A Total Compute solution focused approach enables CoreLink System IP to work seamlessly with Cortex-X CPUs, Cortex-A CPUs, and Ethos NPUs.

Corelink CI-700

Features

The CoreLink CI-700 includes a range of features:

Designed and optimized for premium smartphones and laptops.

  • Based on high-performance AMBA CHI mesh interconnect technology
  • Fully coherent interconnect supports from one to eight coherency clusters over AMBA CHI interface

High bandwidth and low latency from high frequency implementation

  • Supports low power implementations from 1GHz up to high performance implementations up to 2GHz in 5nm processes

Increased performance and lower system power due to the configurable unified system level cache 

  • System level cache reduces average memory latency and reduces system power, because it requires fewer external memory transactions
  • System level cache may be shared with GPU and other accelerators
  • MPAM partitioning enables control of how System level cache resources are allocated and increases predictability
  • Snoop filter avoids the need to broadcast snoops to all CPU clusters
  • Exclusive System level cache: data cached in the CPU cluster is not duplicated in the System level cache
  • System level cache can reduce cost or power of a memory system, for example LPDDR instead of DDR in laptops

Improved security

  • Adopts latest Armv9 architecture features
  • Interface standards focus on security, performance, reliability, and virtualization
  • Memory Tagging Extensions (MTE) for increased security
  • AMBA CHI.E and AMBA AXI.H for Armv9 architecture, security, and virtualization support

Direct System Attach (DSA-F) configuration

  • Removes System Level Cache and snoop filter from CI-700, uses L3 in DynamIQ Shared Unit
  • Implements MTE tag splitter and tag cache

Designed together with the Armv9 processors and latest Arm technologies to provide an optimized Total Compute solution

  • Designed, verified and optimized together as part of a solution focused on the latest premium mobile use-cases
  • Scalable from mainstream smartphone through premium smartphone up to laptops
  • Comprehensive tooling
  • Market-proven in high performance segments such as Servers