Getting Started

The Arm CoreLink CMN-600 Coherent Mesh Network is designed for intelligent connected systems across a wide range of applications including networking infrastructure, storage, server, HPC, automotive, and industrial solutions.  The highly scalable mesh is optimized for Armv8-A processors and can be customized across a wide range of performance points. 

Notable highlights include:

  • Build more powerful infrastructure SoCs from edge to cloud.

  • 5x throughput uplift compared to today’s solution.

  • Coherent mesh interconnect with integrated agile system cache.


Specifications

Feature  Details  
AMBA specifications AMBA 5 CHI
Scalable mesh network Custom sizing and device placement  
Fully coherent CHI slave interfaces

1-32 fully coherent requesters, for example up to 128 Armv8-A processors

Agile System Cache 0MB-128MB shared between compute, accelerators, and IO
IO Coherent slave interface 1-96 IO interfaces
Memory and system master interfaces 1-8 memory interfaces
1-8 system interfaces
Coherency and snoop filter Integrated snoop filter reduces processor core snoops, and reduces system power
Coherent multichip links Extend coherency to multichip supporting the CCIX standard


CMN-600 key features

High performance, scalable coherent mesh 

The scalable mesh network can be customized to meet system performance and area requirements. The native AMBA 5 CHI network provides high-frequency, non-blocking data transfers between compute, accelerator, and IO to shared memory resources.  

  • Custom, automated design with CoreLink Creator
  • Minimum size less than 1mm2 in 16nm
  • Frequencies greater than 2.5GHz
  • Coherent multichip link extends coherency off-chip

Agile system cache

Keeping data on-chip greatly improves performance and efficiency. The integrated agile system cache was designed to boost IO throughput workloads such as networking and storage.

  • Shared cache for compute, accelerators, and IO.
  • Intelligent cache stashing allows accelerators and IO peripherals to allocate critical data to any cache level.
  • Far atomic operations supported within the Agile System Cache to enable high frequency updates of shared data such as counters.  
  • Programmable on-chip scratch pad RAM partitioning options allow applications to lock down critical data structures such as counters, statistics, and tables.      

Optimized for system performance

The CoreLink CMN-600 has been designed with the CoreLink DMC-620 to provide the highest performance coherent backplane for Armv8-A systems from small, efficient access points to data center solutions maximizing compute density. Notable highlights include:

  • 7.5x more compute.
  • 5x higher throughput.
  • 50% lower latency.
  • Sustainable bandwidth exceeding 1TB/s.

CoreLink Creator reduces SoC integration time

CoreLink Creator guides designers through the configuration and creation of an optimized and viable CoreLink CMN-600 interconnect fabric.

It addresses the most complex challenges associated with Interconnect configurability and assembly and enables a faster and easier design that produces a higher quality interconnect.

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Blogs

Community Forums

Not answered CHI protocol cache line states
  • AMBA 5 CHI
  • SoC Verification
0 votes 451 views 0 replies Started 3 days ago by S_Seth Answer this
Not answered STM32F769i-Discovery IP Camera Interface 0 votes 358 views 0 replies Started 4 days ago by Kiran bhat Answer this
Suggested answer Store operations where the cache line is already cached (ACE protocol)
  • AMBA
  • AMBA 4
  • AXI
  • Interface
2 votes 6465 views 9 replies Latest 4 days ago by het Answer this
Not answered Best most recent text on ARM arch 0 votes 406 views 0 replies Started 7 days ago by d.ry Answer this
Not answered Readunique and cleanunique transactions in ACE protocol
  • AMBA
  • AMBA 4
  • AXI4
0 votes 360 views 0 replies Started 7 days ago by het Answer this
Suggested answer Raspberry pi 3 and .net 5 coreclr 1 votes 2290 views 2 replies Latest 8 days ago by delinaty Answer this
Not answered CHI protocol cache line states Started 3 days ago by S_Seth 0 replies 451 views
Not answered STM32F769i-Discovery IP Camera Interface Started 4 days ago by Kiran bhat 0 replies 358 views
Suggested answer Store operations where the cache line is already cached (ACE protocol) Latest 4 days ago by het 9 replies 6465 views
Not answered Best most recent text on ARM arch Started 7 days ago by d.ry 0 replies 406 views
Not answered Readunique and cleanunique transactions in ACE protocol Started 7 days ago by het 0 replies 360 views
Suggested answer Raspberry pi 3 and .net 5 coreclr Latest 8 days ago by delinaty 2 replies 2290 views