Getting Started

The Arm CoreLink CMN-600 Coherent Mesh Network is designed for intelligent connected systems across a wide range of applications including networking infrastructure, storage, server, HPC, automotive, and industrial solutions.  The highly scalable mesh is optimized for Armv8-A processors and can be customized across a wide range of performance points. 

Notable highlights include:

  • Build more powerful infrastructure SoCs from edge to cloud.

  • 5x throughput uplift compared to today’s solution.

  • Coherent mesh interconnect with integrated agile system cache.


Specifications

Feature  Details  
AMBA specifications AMBA 5 CHI
Scalable mesh network Custom sizing and device placement  
Fully coherent CHI slave interfaces

1-32 fully coherent requesters, for example up to 128 Armv8-A processors

Agile System Cache 0MB-128MB shared between compute, accelerators, and IO
IO Coherent slave interface 1-96 IO interfaces
Memory and system master interfaces 1-8 memory interfaces
1-8 system interfaces
Coherency and snoop filter Integrated snoop filter reduces processor core snoops, and reduces system power
Coherent multichip links Extend coherency to multichip supporting the CCIX standard


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    Ensuring the demands of video streaming are consistently met while minimizing cost and maximizing battery life are the challenges for today's SoC designer. This paper explores how QoS mechanisms can enable lower latency while maintaining sufficient overall system bandwidth.

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  • Quality of Service (QoS) in Arm Systems: An Overview

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  • System Validation at Arm

    Enabling Partners to Build Better Systems

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CMN-600 key features

High performance, scalable coherent mesh 

The scalable mesh network can be customized to meet system performance and area requirements. The native AMBA 5 CHI network provides high-frequency, non-blocking data transfers between compute, accelerator, and IO to shared memory resources.  

  • Custom, automated design with CoreLink Creator
  • Minimum size less than 1mm2 in 16nm
  • Frequencies greater than 2.5GHz
  • Coherent multichip link extends coherency off-chip

Agile system cache

Keeping data on-chip greatly improves performance and efficiency. The integrated agile system cache was designed to boost IO throughput workloads such as networking and storage.

  • Shared cache for compute, accelerators, and IO.
  • Intelligent cache stashing allows accelerators and IO peripherals to allocate critical data to any cache level.
  • Far atomic operations supported within the Agile System Cache to enable high frequency updates of shared data such as counters.  
  • Programmable on-chip scratch pad RAM partitioning options allow applications to lock down critical data structures such as counters, statistics, and tables.      

Optimized for system performance

The CoreLink CMN-600 has been designed with the CoreLink DMC-620 to provide the highest performance coherent backplane for Armv8-A systems from small, efficient access points to data center solutions maximizing compute density. Notable highlights include:

  • 7.5x more compute.
  • 5x higher throughput.
  • 50% lower latency.
  • Sustainable bandwidth exceeding 1TB/s.

CoreLink Creator reduces SoC integration time

CoreLink Creator guides designers through the configuration and creation of an optimized and viable CoreLink CMN-600 interconnect fabric.

It addresses the most complex challenges associated with Interconnect configurability and assembly and enables a faster and easier design that produces a higher quality interconnect.

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Blogs

Community Forums

Not answered Aligned and unaligned word transfers on a 64-bit bus
  • AXI
  • AXI4
0 votes 331 views 0 replies Started 5 days ago by Maria_d Answer this
Suggested answer CMSIS: Storage interface vs Flash interface - what's the difference ?
  • CMSIS
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0 votes 539 views 1 replies Latest 5 days ago by Vladimir Umek Answer this
Suggested answer What SBCs I need to choose?
  • Raspberry Pi
  • Maker Faire
  • Single Board Computer (SBC)
  • Development Boards
0 votes 522 views 1 replies Latest 6 days ago by Andy Neil Answer this
Not answered Does anyone knows why a documentation as ARM DSU 0030 is only available for licensees 0 votes 450 views 0 replies Started 7 days ago by JaWa Answer this
Suggested answer The meanings of AxCACHE 0 votes 522 views 1 replies Latest 9 days ago by Christopher Tory Answer this
Suggested answer CoreLink NIC-400 Interconnect gives an extra request
  • CoreLink NIC-400 Network Interconnect
0 votes 608 views 1 replies Latest 9 days ago by Christopher Tory Answer this
Not answered Aligned and unaligned word transfers on a 64-bit bus Started 5 days ago by Maria_d 0 replies 331 views
Suggested answer CMSIS: Storage interface vs Flash interface - what's the difference ? Latest 5 days ago by Vladimir Umek 1 replies 539 views
Suggested answer What SBCs I need to choose? Latest 6 days ago by Andy Neil 1 replies 522 views
Not answered Does anyone knows why a documentation as ARM DSU 0030 is only available for licensees Started 7 days ago by JaWa 0 replies 450 views
Suggested answer The meanings of AxCACHE Latest 9 days ago by Christopher Tory 1 replies 522 views
Suggested answer CoreLink NIC-400 Interconnect gives an extra request Latest 9 days ago by Christopher Tory 1 replies 608 views