CMN-600AE key features
Functional safety capability
The CMN-600AE is designed to meet the automotive safety requirements for building high performance ASIL B to ASIL D systems. It uses a highly optimized architecture that implements redundancy, while minimizing area using protected shared memories. The CMN-600AE provides fault detection and correction features that meet the highest safety requirements of systems up to ASIL D, including:
- Integrated resilience and functional safety with ECC on shared integrated RAMs, CRC protection on transport, timeouts, memory protection unit and resource isolation.
- Enhanced device management capabilities with fault management unit.
- Extended safety documentation package (for systems up to ASIL D).
High performance scalable coherent mesh
The scalable mesh network can be customized to meet system performance and area requirements. The native AMBA 5 CHI network provides high-frequency, non-blocking data transfers between compute, accelerator, and IO to shared memory resources.
- Custom, automated design with CoreLink Creator.
- Minimum size less than 1mm² in 16nm.
- Frequencies greater than 2.5GHz.
- Coherent multichip link extends coherency off-chip.
Agile system cache
Keeping data on-chip greatly improves performance and efficiency. The integrated agile system cache was designed to boost high throughput workloads, such as computer vision processing and neural networks.
- Shared cache for compute, accelerators, and IO.
- Intelligent cache stashing allows accelerators and IO peripherals to allocate critical data to any cache level.
- Far atomic operations supported within the Agile System Cache to enable high frequency updates of shared data such as counters.
- Programmable on-chip scratch pad RAM partitioning options allow applications to lock down critical data structures such as counters, statistics, and tables.
Coherent Multichip Links
The Coherent Multichip Links (CML) of the CMN-600AE allow the extension of the high frequency, non-blocking AMBA 5 CHI protocol messages across multiple SoCs, enabling system designers to attach more compute or acceleration with a shared virtual memory.
The multichip links also support CCIX, the open coherency standard that allows processors based on different instruction set architectures to extend the benefits of cache coherent, peer processing to acceleration devices including FPGAs, GPUs, network/storage adapters, intelligent networks and custom ASICs. For more information, see www.ccixconsortium.com.
CoreLink Creator reduces SoC integration time
CoreLink Creator guides designers through the configuration and creation of an optimized and viable CMN-600AE interconnect fabric.
It addresses the most complex challenges associated with interconnect configurability and assembly and enables a faster and easier design that produces a higher quality interconnect.
