Getting Started

The Arm CoreLink CMN-600AE (Automotive Enhanced) Coherent Mesh Network is designed for high performance automotive systems across a wide range of applications including In-vehicle Infotainment (IVI), digital cockpit, Advanced Driver-Assistance Systems (ADAS) and autonomous driving systems.  The highly scalable mesh is optimized for Armv8-A processors and can be customized across a wide range of performance points.

CMN-600AE is part of Arm's Safety Ready program, a collection of products across the Arm portfolio that have been through various and rigorous levels of functional safety systematic flows and development.

Notable highlights include:

  • Ability to build more scalable, power efficient automotive SoCs from ADAS to autonomous driving.

  • Coherent mesh interconnect with integrated agile system cache and integrated coherent multichip support.

  • Integrated resilience and functional safety features, with enhanced device management capabilities. 

  • Extended safety documentation package (systems up to ASIL D).


Specifications

Feature  Details  
AMBA specifications AMBA 5 CHI with extensions for interface protection 
Scalable mesh network Custom sizing and device placement
Fully coherent CHI slave interfaces 1-8 fully coherent requesters, for example up to 64 Armv8-A processors
Agile system cache 0MB-32MB shared between compute, accelerators, and IO
IO coherent slave interface 1-24 IO interfaces
Memory and system master interfaces 1-4 memory interfaces
1-4 system interfaces
Coherency and snoop filter Integrated snoop filter reduces processor core snoops, and reduces system power
Coherent multichip links Extend coherency to multichip supporting the CCIX standard
Integrated resilience and functional safety Integrated RAM with ECC, CRC protection on transport, transaction error detection and memory protection unit

CMN-600AE key features

Automotive enhanced scalable coherent mesh

The CMN-600AE is designed to meet the automotive safety requirements for building high performance ASIL B to ASIL D systems. It uses a highly optimized architecture that implements redundancy, while minimizing area using protected shared memories. The CMN-600AE provides fault detection and correction features that meet the highest safety requirements of systems up to ASIL D, including:

  • Integrated resilience and functional safety with ECC on shared integrated RAMs, CRC protection on transport, timeouts, memory protection unit and resource isolation.
  • Enhanced device management capabilities with fault management unit.
  • Extended safety documentation package (for systems up to ASIL D).

High performance scalable coherent mesh

The scalable mesh network can be customized to meet system performance and area requirements. The native AMBA 5 CHI network provides high-frequency, non-blocking data transfers between compute, accelerator, and IO to shared memory resources. 

  • Custom, automated design with CoreLink Creator. 
  • Minimum size less than 1mm² in 16nm. 
  • Frequencies greater than 2.5GHz. 
  • Coherent multichip link extends coherency off-chip.

Agile system cache

Keeping data on-chip greatly improves performance and efficiency. The integrated agile system cache was designed to boost high throughput workloads, such as computer vision processing and neural networks. 

  • Shared cache for compute, accelerators, and IO. 
  • Intelligent cache stashing allows accelerators and IO peripherals to allocate critical data to any cache level. 
  • Far atomic operations supported within the Agile System Cache to enable high frequency updates of shared data such as counters.   
  • Programmable on-chip scratch pad RAM partitioning options allow applications to lock down critical data structures such as counters, statistics, and tables.

Coherent Multichip Links

The Coherent Multichip Links (CML) of the CMN-600AE allow the extension of the high frequency, non-blocking AMBA 5 CHI protocol messages across multiple SoCs, enabling system designers to attach more compute or acceleration with a shared virtual memory.

The multichip links also support CCIX, the open coherency standard that allows processors based on different instruction set architectures to extend the benefits of cache coherent, peer processing to acceleration devices including FPGAs, GPUs, network/storage adapters, intelligent networks and custom ASICs. For more information, see www.ccixconsortium.com.

CoreLink Creator reduces SoC integration time

CoreLink Creator guides designers through the configuration and creation of an optimized and viable CMN-600AE interconnect fabric.

It addresses the most complex challenges associated with interconnect configurability and assembly and enables a faster and easier design that produces a higher quality interconnect.

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Forums

Not answered what action will be performed by the master based on the read and write responce in axi 4?
  • AXI
  • AXI4
0 votes 20 views 0 replies Started 8 hours ago by Hem Patel Answer this
Answered ACE protocol : Eviction and snoop request at same time
  • AMBA
  • l1
  • ACE
  • cache
0 votes 345 views 1 replies Latest 8 days ago by Christopher Tory Answer this
Suggested answer AXI3 write data interleaving with same AWID
  • AMBA
  • AXI
0 votes 413 views 4 replies Latest 8 days ago by mveereshm622 Answer this
Suggested answer AHB revisions from AHB3 to AHB5
  • AMBA
  • AHB
0 votes 153 views 1 replies Latest 9 days ago by Colin Campbell Answer this
Suggested answer Burst termination with BUSY transfer on AHB
  • AMBA
  • AHB
0 votes 131 views 1 replies Latest 9 days ago by Colin Campbell Answer this
Suggested answer Regarding retry response
  • AMBA
  • AHB
0 votes 124 views 1 replies Latest 9 days ago by Colin Campbell Answer this
Not answered what action will be performed by the master based on the read and write responce in axi 4? Started 8 hours ago by Hem Patel 0 replies 20 views
Answered ACE protocol : Eviction and snoop request at same time Latest 8 days ago by Christopher Tory 1 replies 345 views
Suggested answer AXI3 write data interleaving with same AWID Latest 8 days ago by mveereshm622 4 replies 413 views
Suggested answer AHB revisions from AHB3 to AHB5 Latest 9 days ago by Colin Campbell 1 replies 153 views
Suggested answer Burst termination with BUSY transfer on AHB Latest 9 days ago by Colin Campbell 1 replies 131 views
Suggested answer Regarding retry response Latest 9 days ago by Colin Campbell 1 replies 124 views