The Arm CoreLink CMN-700 Coherent Mesh Network is a high bandwidth, low-latency system interconnect that supports a wide range of applications. The application supported includes networking infrastructure, storage, server, HPC, automotive, and industrial solutions. The highly scalable mesh is optimized for Armv8.2 to Armv9.0 CPUs and can be customized across a wide range of performance, power, and area requirements.
|AMBA specifications||AMBA 5 CHI Issue-B, -C, -D, and -E; AXI5/ACE5-Lite; and CXS for multi-chip|
|Scalable mesh network||Up to 12x12 mesh size with single and dual data paths|
|Fully coherent CHI slave interfaces||0 - 128 coherent cluster of CPUs or accelerators per die, 512 total|
|Agile System Cache||0 - 128 system cache instances for 0 - 512MB shared cache per mesh|
|Memory and system master interfaces||0 - 40 single or dual channel memory controllers|
|IO Coherent Requester interface||1 - 40 I/O nodes supporting up to 120 AXI5/ACE5-lite interfaces|
|IO Responder interfaces||1 - 32 I/O nodes supporting ACE-Lite ports, optimized for PCIe peer-to-peer|
|Coherency and snoop filter||Distributed snoop filter with perfect match up to 128 cores or DSUs|
|Coherent multichip links||Up to 32 CCIX or CXL gateways for SMP links, memory, or accelerators|
The following diagram shows some key features and scalability of the CMN-700 interconnect. Using the Socrates Creator tool, developers can compose topologies from as little as 2 cross-points (XPs) with 8 device ports to very large single and multi-chip configurations.
The CoreLink CMN-700 includes a range of features:
Highest performing, scalable coherent mesh
This scalable mesh network can be customized to meet system performance and area requirements. The native AMBA 5 CHI device ports provide high-frequency, non-blocking data transfers between compute, accelerator, I/O, and shared memory resources.
- Custom topologies and sizing with Socrates
- Memory congestion feedback to CPUs
- Frequencies greater than 2.5GHz
- CXL, CCIX, and SMP gateways for coherency off-chip
Agile system cache
The system cache provides CPUs and I/O requesters a distributed, scalable, low-latency, high-bandwidth SRAM for evicted or stashed data. Improvements over the previous generation include:
- Non-power-of-2 number of instances to support a range of CPUs and core counts.
- Striping or hashing across non-power-of-2 number of memory controllers and CXL memory
- Memory write congestion feedback mechanism to requesting CPUs.
- Software-managed cache allocation and monitoring per operating system P\process/thread through MPAM.
- Per-cache line Memory Tag Extension (MTE) to detect access errors.
Socrates Creator reduces SoC development time
Socrates guides designers through the configuration of the CMN-700 interconnect fabric and creation of optimized, error-free RTL. It addresses the most complex challenges associated with interconnect configurability and assembly and enables a faster and easier design that produces a higher-quality interconnect.
Optimized for system performance
The Neoverse CMN-700 is designed to scale from a small PCIe or CXL device to multi-chip SoCs for high-performance computing. Notable improvements over the previous generation include:
- PCIe-Gen5 support
- 3x increase in cross section bandwidth
- 6x increase in memory bandwidth
- 14x increase in chip-to-chip bandwidth
- 35% lower chip-to-chip latency