Getting Started

The Arm CoreLink Network Interconnect offers highly configurable topology with Network on Chip (NoC)-like properties that enable you to build high performance, optimized, AMBA-compliant SoC connectivity. CoreLink Network Interconnect is configurable across a wide range of applications from a single bridge component, for example an AHB to AXI protocol bridge, to a complex infrastructure that consists of up to 128 masters and 64 slaves in a combination of different AMBA protocols.

  • CoreLink NIC-450 Network Interconnect Chip.

  • CoreLink NIC-450

    • Library of key interconnect IP that enables designers to build a scalable and configurable network interconnect
    • Available with a new tooling automation flow using CoreLink Creator that employs algorithms to accelerate configuration based on design requirements
    • Enables integrated tooling environment using CoreLink Creator and Socrates DE (licensed separately) for configuring complex interconnect subsystem designs.
    • Includes all NIC-400 features
  • CoreLink NIC-400 Network Interconnect Chip.

  • CoreLink NIC-400

    • Fully configurable, hierarchical, low latency, low power connectivity for AMBA 4 AXI4, AXI3, AHB-Lite and APB interfaces.
    • Scalable for multiple applications from simple single core designs, up to large coherent systems as a companion to CoreLink CCI and CCN coherent interconnects.

    NIC-400 TRM

NIC-450 and CoreLink Creator

CoreLink Creator with its harvesting flows and enhanced tooling environment provides significant improvements to configure NICs, which decreases time to market.

Functional enhancement in NIC-400r1 with QVN-terminate feature to resolve head-of-line blocking when accessing DRAM provide:

  • Improved support for QVN with DMC controllers using sideband QOSACCEPT signaling, supported in DMC-500 and other 3rd party DMC providers.

  • CPU latency reduction with QoS enhancements, designed and tested with Arm memory controllers such as CoreLink DMC-500.

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CoreLink ADB-400

The CoreLink ADB-400 AMBA Domain Bridge is an asynchronous bridge between two components or systems that can be in a different power, clock, or voltage domains.

The ADB-400 supports:

  • An optional configurable destination register for the payload of each channel.
  • Simple reset requirements.
  • A power management interface.
  • Dynamic Voltage and Frequency Scaling (DVFS).
  • Quality of Service (QoS) Virtual Network (QVN).
  • Clock status indication.

The ADB-400 consists of a slave domain and a master domain. The slave domain received transfers from the AMBA master and the master domain transmits transfers to an AMBA slave.

CoreLink XHB-400

The XHB converts AXI4 protocol to AHB-Lite protocol and has an AXI4 slave interface and an AHB-Lite master interface. 

AXI4 slave interface: This connects to either the AXI4 master interface of a processor or to an AXI interconnect.

AHB-Lite master interface: This implements an AHB-Lite master to drive AHB-Lite subsystems.

Click to view the XHB-400 TRM

NIC-450 Library of Interconnect IP

Network Interconnect NIC-400
Advanced Quality of Service QoS-400
 Virtual Networks QVN-400
 Thin Links TLX-400
 AMBA Domain Bridge ADB-400
 AXI-to-AHB Bridge XHB-400
 Low-power distributor LPD-500

Resources

Useful Information

Documents and blogs that will help users design Arm-based SoCs

AMBA Specifications

System Validation at Arm: Enabling Partners to Build Better Systems

Quality of Service (QoS) in Arm Systems: An Overview

QoS for High-Performance and Power-Efficient HD ... - Arm

Introduction to QoS Virtual Networks (QVN)

 

Arm Connected Community

NIC Technical Articles



Related Products

Arm System IP is designed and optimized to be used with other Arm IP and tools

CoreLink Cache Coherent Interconnect

CoreLink Cache Coherent Network

Cortex Processors

Memory Controllers

System Controllers

System IP Tooling

 

 

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Community Forums

Not answered AXI fixed burst to a slave with narrow data width
  • AXI
  • AXI4
  • Bus Architecture
 0 votes 20 views 0 replies Started yesterday by Sana Answer this
Suggested answer NOR, SPI, U-Boot, Kernal 0 votes 93 views 2 replies Latest 2 days ago by Andy Neil Answer this
Answered Regarding implementation of a scenario in AHB protocol 0 votes 142 views 4 replies Latest 3 days ago by Suyash Sharma Answer this
Suggested answer How could CMN600 route snoop transactions to RN-F 0 votes 333 views 2 replies Latest 4 days ago by Joe Chen Answer this
Suggested answer Application scenarios of APB4 0 votes 346 views 1 replies Latest 5 days ago by Christopher Tory Answer this
Suggested answer Outstanding support in AXI slave 0 votes 293 views 1 replies Latest 5 days ago by Christopher Tory Answer this
Not answered AXI fixed burst to a slave with narrow data width Started yesterday by Sana 0 replies 20 views
Suggested answer NOR, SPI, U-Boot, Kernal Latest 2 days ago by Andy Neil 2 replies 93 views
Answered Regarding implementation of a scenario in AHB protocol Latest 3 days ago by Suyash Sharma 4 replies 142 views
Suggested answer How could CMN600 route snoop transactions to RN-F Latest 4 days ago by Joe Chen 2 replies 333 views
Suggested answer Application scenarios of APB4 Latest 5 days ago by Christopher Tory 1 replies 346 views
Suggested answer Outstanding support in AXI slave Latest 5 days ago by Christopher Tory 1 replies 293 views