Getting Started

The Arm CoreLink Network Interconnect (NIC) family offers highly configurable topology that enable you to build high performance, optimized, AMBA-compliant SoC connectivity. The CoreLink NIC family is configurable across a wide range of applications from a single bridge component, for example an AHB to AXI protocol bridge, to complex consumer and infrastructure applications.

CoreLink NI-700

NI-700 configurable and scalable Network-on-Chip

Network-on-Chip (NoC) for high-bandwidth accelerators, rest-of-SoC connectivity, and peripherals. A companion to Corelink CI-700 coherent interconnect.

Scalable and highly configurable network-on-chip (NoC)

  • Flexible packetized network-on-chip (NoC) for high-bandwidth accelerators such as GPU and NPU, as well as rest-of-SoC connectivity and peripherals.
  • Suited to infrastructure, as well as consumer and embedded applications.
  • Supports integrated clock controller and power domain settings to manage all the internal P/Q channels

Improved security and performance

  • Adopts the latest Arm architectural features and AMBA protocols that focus on security, performance, reliability, and virtualization.
  • NI-700 supports AHB natively and does not need an AXI to AHB bridge along with integrated QoS features.
  • NI-700 is a natively packetized interconnect and hence inherently more scalable with respect to wiring congestion (variable flit sizes) and timing closure.

Advanced tooling

  • Faster design, configuration, integration, and implementation of complex SoCs for improved system performance, and reduced routing congestion and area.
  • Floorplan and traffic aware AI technology generates and optimizes a NoC speeding time-to-market with improved results.
CoreLink NI-700 TRM
  • CoreLink NIC-450 Network Interconnect Chip.

  • CoreLink NIC-450

    • Library of key interconnect IP that enables designers to build a scalable and configurable NIC.
    • Available with a tooling automation flow using CoreLink Creator that employs algorithms to accelerate configuration based on design requirements.
    • Enables integrated tooling Socrates DE (licensed separately) for configuring complex interconnect subsystem designs.
    • Includes all NIC-400 features.
    NIC-450 TRM
  • CoreLink NIC-400 Network Interconnect Chip.

  • CoreLink NIC-400

    • Fully configurable, hierarchical, low latency, low power connectivity for AMBA 4 AXI4, AXI3, AHB-Lite and APB interfaces.
    • Scalable for multiple applications from simple single core designs, up to large coherent systems as a companion to CoreLink CCI and CCN coherent interconnects.

    NIC-400 TRM

NIC-450 and CoreLink Creator

CoreLink Creator with its harvesting flows and enhanced tooling environment provides significant improvements to configure NICs, which decreases time to market.

Functional enhancement in NIC-400r1 with QVN-terminate feature to resolve head-of-line blocking when accessing DRAM provide:

  • Improved support for QVN with DMC controllers using sideband QOSACCEPT signaling, supported in DMC-500 and other 3rd party DMC providers.
  • CPU latency reduction with QoS enhancements, designed and tested with Arm memory controllers such as CoreLink DMC-500.

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

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CoreLink ADB-400

The CoreLink ADB-400 AMBA Domain Bridge is an asynchronous bridge between two components or systems that can be in a different power, clock, or voltage domains.

The ADB-400 supports:

  • An optional configurable destination register for the payload of each channel.
  • Simple reset requirements.
  • A power management interface.
  • Dynamic Voltage and Frequency Scaling (DVFS).
  • Quality of Service (QoS) Virtual Network (QVN).
  • Clock status indication.

The ADB-400 consists of a slave domain and a master domain. The slave domain received transfers from the AMBA master and the master domain transmits transfers to an AMBA slave.

CoreLink XHB-400

The XHB converts AXI4 protocol to AHB-Lite protocol and has an AXI4 slave interface and an AHB-Lite master interface. 

AXI4 slave interface: This connects to either the AXI4 master interface of a processor or to an AXI interconnect.

AHB-Lite master interface: This implements an AHB-Lite master to drive AHB-Lite subsystems.

XHB-400 TRM

NIC-450 Library of Interconnect IP

Network Interconnect NIC-400
Advanced Quality of Service QoS-400
 Virtual Networks QVN-400
 Thin Links TLX-400
 AMBA Domain Bridge ADB-400
 AXI-to-AHB Bridge XHB-400
 Low-power distributor LPD-500

Resources

Useful Information

Documents and blogs that will help users design Arm-based SoCs

AMBA Specifications

System Validation at Arm: Enabling Partners to Build Better Systems

Quality of Service (QoS) in Arm Systems: An Overview

QoS for High-Performance and Power-Efficient HD ... - Arm

Introduction to QoS Virtual Networks (QVN)

Related Products

Arm System IP is designed and optimized to be used with other Arm IP and tools

CoreLink Cache Coherent Interconnect

CoreLink Cache Coherent Network

Cortex Processors

Memory Controllers

System Controllers

System IP Tooling

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Not answered HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2) 0 votes 27 views 0 replies Started 8 hours ago by Tapas Answer this
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Suggested answer How to calculate AXI interleave depth and reorder depth.
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Answered One master to two slave transfer (back to back) behavior for address A (slave1) and address B (slave2) 0 votes 219 views 1 replies Latest 4 days ago by Colin Campbell Answer this
Answered Forum FAQs Started 8 months ago by Annie 0 replies 5199 views
Answered Forum FAQs Started 8 months ago by Annie 0 replies 4555 views
Not answered HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2) Started 8 hours ago by Tapas 0 replies 27 views
Not answered A power electronics controls in C/C++ embedded and software pointer for PC program Started 15 hours ago by Md Mubdiul 0 replies 32 views
Suggested answer How to calculate AXI interleave depth and reorder depth. Latest 3 days ago by Koalassy 3 replies 3748 views
Answered One master to two slave transfer (back to back) behavior for address A (slave1) and address B (slave2) Latest 4 days ago by Colin Campbell 1 replies 219 views