A set of configurable AMBA AXI5 security-aware system IP components

The CoreLink SIE-300 AMBA AXI5 system IP includes a set of configurable AMBA AXI5 components to protect peripherals and memories from Non-trusted masters. It also includes an AMBA AXI5 SRAM memory controller and bridges to manage clock and power domain boundary crossings. The system IP is compatible with Cortex-M55 based systems with TrustZone technology, which offers a system-wide approach to security with hardware-enforced isolation.

  • Reduces cost and increases security in Cortex-M55 based systems with TrustZone for IoT and embedded applications.
  • Makes it easier and more efficient to create secure systems or to build a system around an existing TrustZone-enabled subsystem
  • Provides flexibility due to its configurability and fine-grained block-based Secure and Non-secure partition setting

CoreLink SIE-300 is a part of Arm Corstone-300, a reference package that helps designers build secure SoCs quickly.


CoreLink SIE-300 consists of the following components:

Master Security Controller (MSC)
The MSC acts as security gate for AXI transactions, and it can transform the security attribute.

Memory Protection Controller (MPC)
The MPC acts as security gate for AXI transactions that target a memory interface. The security checks operate on block or page level, and are programmable by using the APB slave interface.

Peripheral Protection Controller (PPC)
The PPC gates AXI5 transactions to, and responses from, peripherals when a security violation occurs.

Access Control Gate (ACG)
The ACG component can be placed on a clock or power domain boundary to pass or block AXI5 transactions whenever the downstream component cannot accept the transaction or is explicitly asked not to do so. The transaction is latched internally and the ACG generates automatic responses when necessary.

Sync-Down Bridge (SDB)
The SDB synchronizes AXI5 interfaces where the upstream side is faster than the downstream side and the clocks are synchronous, in phase and have an N:1 frequency ratio.

Sync-Up Bridge (SUB)
The SUB synchronizes AXI5 interfaces where the upstream side is slower than the downstream side and the clocks are synchronous, in phase, and have a 1:N frequency ratio.

SRAM Memory Controller (SMC)
The SMC enables on-chip synchronous RAM blocks to attach to an AXI5 interface. The SMC supports 32, 64, 128, or 256-bit SRAM with byte writes.