The CoreLink XHB-500 is a low latency bridge that efficiently connects an AMBA AXI5 to the AHB5 bridge and an AHB5 to the AXI5 bridge. The bridge translates AXI5 or AHB5 transactions into the corresponding AHB or AXI transfers. CoreLink XHB-500:

  • Connects both AXI and AHB systems to enable a combination of Cortex-A, Cortex-R and Cortex-M-based elements
  • Includes AXI to AHB and AHB to AXI bridging and allows for synchronous crossing for fast operations.
  • Provides maximum flexibility with many configuration points including a bus size from 32bits to 1024bits, buffering, power control, TrustZone security attributes and more.

Features

AXI5 to AHB5 Bridge

AX15 to AHB5 Bridge block diagram

The AXI5 to AHB5 bridge is a low-latency bridge that performs no transaction buffering. The main features of this bridge include:

  • Single power domain
  • Single clock domain
  • Configurable data width
  • AXI5 slave interface features:
    • AXI5 protocol support
    • AXI4 protocol support
    • Fixed address width
    • Registered or unregistered interface
    • Single Exclusive accesses. Exclusive bursts are not supported.
    • Unaligned accesses
    • Conversion of sparse write transactions, when the HWSTRB_ENABLE configuration parameter is set to OFF
    • Supports all burst types
  • AHB5 master interface features:
    • AHB5 support
    • AHB-Lite support, which requires several signals to be tied off
    • Fixed address width
    • Registered or unregistered interface
    • Exclusive accesses. For AHB-Lite, extra glue logic is required.
    • Write strobe support using the hwstrb signal, when the HWSTRB_ENABLE configuration parameter is set to ON. The hwstrb signal is not present in the Arm AMBA 5 AHB Protocol Specification.
  • Q-Channel interface for clock control
  • Q-Channel interface for power control

 

AHB5 to AXI5 Bridge

AHB5 to AX15 Bridge block diagram

The AHB5 to AXI5 bridge is a low-latency bridge. The main features of this bridge include:

  • Single power domain
  • Single clock domain
  • Configurable data width
  • AHB5 slave interface features:
    • AHB5 protocol support
    • Fixed address width
    • Registered or unregistered interface
    • Support for early write response
    • Supports all burst types
  • AXI5 master interface features:
    • AXI5 support
    • Fixed address width
    • Registered or unregistered interface
    • RAW hazard checking for early write response
    • Buffered write error interrupt
    • Q-Channel interface for clock control
    • Q-Channel interface for power control

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