Getting Started

Arm CoreSight technology is a set of tools that can be used to debug and trace software that runs on Arm-based SoCs. Debugging features are used to observe or modify the state of parts of the design, while trace features allow for continuous collection of system information for later off-line analysis. With CoreSight, both are used together at all stages in the design flow.

  • CoreSight Soc-600 Chip.
  • CoreSight Components

    • CoreSight SoC-600 
    • CoreSight SoC-400
    • System Trace Macrocell
    • Trace Memory Controller
    • CoreSight ELA-500
    • CoreSight ELA-600
    • CoreSight SDC-600
    Find out more
  • A bug (representing debugging).
  • CoreSight Architecture

    • Serial Wire Debug
    • Arm Debug Interface (ADI) Architecture
    • Architecture Specifications
    • High Speed Serial Trace Port

    Find out more

Tools Support

CoreSight debug and trace is fully supported by Arm Development Studio for the bring-up and optimization of SoCs. It is also supported by a wide array of software and hardware debug tools companies, across all markets and regions. Some examples are: 

  • Debug of symmetric multi-processing and asymmetric multicore systems with Arm Development Studio.
  • Powerful interactive debugging with real-time visibility with Green Hills' TimeMachine.
  • Performance optimization using actual best/worst/average execution times at the instruction, block, function and task levels with Streamline.

Highlights 

CoreSight IP provides all the components needed to generate a debug and trace solution that also includes cross trigger and time-stamping distribution capabilities, as well as embedded logic analysis and system trace.

CoreSight SoC components

The CoreSight SoC components provide all the infrastructure required at the SoC level for building a complete debug and trace infrastructure for single and multi-processing units, such as Cortex processors. Arm offers a public CoreSight architecture specification describing standard interfaces and programmer views; this enables developers to integrate their debug and trace solution within the Arm CoreSight solution.

The CoreSight technology offers an exhaustive range of trace macrocells including:

  • CoreSight Embedded Trace Macrocells (ETM)
  • Program Trace Macrocells (PTM)
  • System Trace Macrocell (STM)
  • Trace Memory Controller (TMC)

Customer Successes

Samsung

"Arm CoreSight debug and trace technology was instrumental to the successful bring-up of the Exynos 7870. When designers are working on optimizations to eke out the maximum performance, there is peace of mind in knowing that CoreSight gives the best real-time trace delivering visibility onto the chip fast in order to fine tune the performance" Samsung Exynos 7870

Xilinx

"In addition, Arm CoreSight debug and trace technology was implemented in the chip’s development to provide on-chip visibility that enables fast diagnosis of bugs and performance analysis. Amongst other things, CoreSight ensures it meets the high quality standards required by ISO 26262." Xilinx Zynq-7000


Resources

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Not answered Handshaking for the write data channel 0 votes 16 views 0 replies Started 7 hours ago by Ravi V. Answer this
Not answered Looking for manufacturer to produce our motherboard design 0 votes 31 views 0 replies Started 14 hours ago by Fran Saez Answer this
Suggested answer BUSY transfer and WAIT state both are using the same time ,How to perform the AHB?
  • AHB
0 votes 3713 views 2 replies Latest 2 days ago by Mukul_Prajapati Answer this
Answered Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior
  • AMBA
  • ACE
  • ACE 5
  • interconnect
  • AMBA 5
0 votes 6871 views 6 replies Latest 2 days ago by AlexR Answer this
Suggested answer AXI3 locked access
  • AMBA
  • AXI
0 votes 3089 views 3 replies Latest 3 days ago by Colin Campbell Answer this
Answered Difference btw AXI3 and AXI4
  • AMBA
  • AXI3
  • AXI4
  • Interface
0 votes 11072 views 6 replies Latest 3 days ago by Colin Campbell Answer this
Not answered Handshaking for the write data channel Started 7 hours ago by Ravi V. 0 replies 16 views
Not answered Looking for manufacturer to produce our motherboard design Started 14 hours ago by Fran Saez 0 replies 31 views
Suggested answer BUSY transfer and WAIT state both are using the same time ,How to perform the AHB? Latest 2 days ago by Mukul_Prajapati 2 replies 3713 views
Answered Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior Latest 2 days ago by AlexR 6 replies 6871 views
Suggested answer AXI3 locked access Latest 3 days ago by Colin Campbell 3 replies 3089 views
Answered Difference btw AXI3 and AXI4 Latest 3 days ago by Colin Campbell 6 replies 11072 views