The Arm CoreSight ELA-500 Embedded Logic Analyzer provides an effective way to observe low-level signals, by offering a way to zoom into the root cause of data corruption. You can program the ELA-500 to trigger signal capture in response to a particular event, in addition to causing triggers elsewhere in the SoC to further help with the debug process.
The ELA-500 addresses many of the Design For Test (DFT) methodology requirements, by making products inherently debuggable at all stages of their lifecycle.
Multiple ELAs can be instantiated in a SoC to monitor system signals, each tightly coupled with associated IP, such as a processor or a Cache Coherent Interconnect (CCI). You can create a cross-trigger network alongside these ELAs to send and receive trigger signals, and expanding visibility to the whole SoC. Also, ELA trigger outputs can be used to control clock-gating for a scan dump of registers values.
- Programmable over debug APB using an external debugger or processor for trigger condition setup.
- Generate trigger from one of up to 12 × 128-bit signal groups using assertion-styled conditions.
- Trigger conditions that are built by using trigger state transitions, event counting, comparators for criteria evaluation, and signal masking.
- Trace capture selected signal group in embedded SRAM, configurable size 4k to 64k, for later analysis or waveform capture over time. Supports trace filtering.
- Trigger alongside other ELAs and SoC components over a CoreSight Cross Trigger Interface (CTI).
- Program up to four trigger states in any sequence, including loops.
- Each trigger state can select one of the 12 signal groups as input for trigger conditions.
- Each trigger condition is programmable for comparisons (=, !=, >, >=, <, <=) to mask, and match, any combination of 128 signals.
- Each trigger state has a 32-bit counter input.
- Program up to eight output actions that can be triggered for each trigger state.
CoreSight ELA-500 Technical Reference Manual
For system designers, systems integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.Read here
CoreSight technical introduction
Learn about the basics of Arm CoreSight debug and trace technology, and how to implement it in a system.Read here
Introduction to CoreSight SoC-400
This short video introduces the motivation behind the requirement for debug and trace, and provides an overview of how CoreSight SoC-400 can help build this functionality into SoC designs.Watch video
Better trace for better software with Arm CoreSight
This white paper explores the limitations of existing software debug and trace technologies, and explains how the Arm CoreSight System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, at the same time as applying existing open source trace infrastructures.Read here
Low pin-count debug interfaces for multi-device systems
This white paper examines some alternatives to JTAG as a debug interface, and concludes that a serial wire debug interface can be delivered with lower pin-count and higher performance, and maintain support for multiprocessor systems and interoperability with test.Read here
Key steps to create a debug and trace solution for an Arm SoC
The global cost of debugging software has risen to $312 billion annually. This whitepaper outlines the key steps to create a debug and trace solution for an Arm SoC.Read here
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Documents and blogs that are useful when designing Arm-based SoCs.