Arm CoreSight ELA-600 Embedded Logic Analyzer

CoreSight-ELA 600 Chip.

Getting Started

The CoreSight ELA-600 Embedded Logic Analyzer inherits the debug capability and signal observability features of CoreSight ELA-500 with further optimization to improve data tracing efficiency and capacity. With CoreSight ELA-600, trigger condition can be set to initiate data tracing or output actions.
You also have the option of either storing trace data within CoreSight ELA-600 embedded SRAM in the same manner as CoreSight ELA-500 or aggregating them onto a larger memory area in the system/external to the SoC. 

Benefits

  • Improve low-level signal observability and controllability in post-silicon debug.
  • Shorten debug cycle by speeding up error root-cause analysis.
  • Improve system efficiency with run-time signal monitoring and control.

Specifications

CoreSight ELA-600 allows you to identify hard-to-diagnose bugs quickly. This accelerates silicon bring-up.

ELA-600 schematic diagram showing 12 input group signals and main ELA-600 functions

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

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CoreSight ELA-500 and ELA-600 Comparison

CoreSight ELA-600 gives you additional enhancements that extend existing debug and trace use cases.

Feature ELA-500 ELA-600
Trigger states 5 8
Embedded RAM config  ✔
  ✔
Data compression    ✔
ATB interface    ✔
Simultaneous trace of 2 SIGNALGRPs on same clock cycle    ✔
Trigger state counters tracing    ✔
32-bit segmented trigger state comparators    ✔

  • Manual containing technical information.

  • Technical Reference Manual

    For system designers, systems integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Read here

Resources

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Answered HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2) 0 votes 538 views 2 replies Latest 2 days ago by Tapas Answer this
Answered Forum FAQs Started 8 months ago by Annie 0 replies 5556 views
Answered Forum FAQs Started 8 months ago by Annie 0 replies 4566 views
Not answered Unaligned transfer pattern in AXI4 Started yesterday by Supal 0 replies 117 views
Not answered AHB - continue the transfer after an error response Started yesterday by Joon Hong 0 replies 272 views
Not answered Flash Patching in Cortex M7 Started 2 days ago by SaiGautamJP 0 replies 363 views
Answered HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2) Latest 2 days ago by Tapas 2 replies 538 views