Arm CoreSight ELA-600 Embedded Logic Analyzer

CoreSight-ELA 600 Chip.

Getting Started

The CoreSight ELA-600 Embedded Logic Analyzer inherits the debug capability and signal observability features of CoreSight ELA-500 with further optimization to improve data tracing efficiency and capacity. With CoreSight ELA-600, trigger condition can be set to initiate data tracing or output actions.
You also have the option of either storing trace data within CoreSight ELA-600 embedded SRAM in the same manner as CoreSight ELA-500 or aggregating them onto a larger memory area in the system/external to the SoC. 

Benefits

  • Improve low-level signal observability and controllability in post-silicon debug.
  • Shorten debug cycle by speeding up error root-cause analysis.
  • Improve system efficiency with run-time signal monitoring and control.

Highlights

CoreSight ELA-600 allows you to identify hard-to-diagnose bugs quickly. This accelerates silicon bring-up.

ELA-600 schematic diagram showing 12 input group signals and main ELA-600 functions

CoreSight ELA-500 and ELA-600 Comparison

CoreSight ELA-600 gives you additional enhancements that extend existing debug and trace use cases.

Feature

ELA-500

ELA-600

Trigger states

5

8

Embedded RAM config

✔

✔

Data compression

✔

ATB interface

✔

Simultaneous trace of 2 SIGNALGRPs on same clock cycle

✔

Trigger state counters tracing

✔

32-bit segmented trigger state comparators

✔

  • Manual containing technical information.

  • Technical Reference Manual

    For system designers, systems integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Read here

Resources

Get support

Arm support

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Community Forums

Not answered what action will be performed by the master based on the read and write responce in axi 4?
  • AXI
  • AXI4
 0 votes 20 views 0 replies Started 7 hours ago by Hem Patel Answer this
Answered ACE protocol : Eviction and snoop request at same time
  • AMBA
  • l1
  • ACE
  • cache
 0 votes 345 views 1 replies Latest 8 days ago by Christopher Tory Answer this
Suggested answer AXI3 write data interleaving with same AWID
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  • AXI
 0 votes 412 views 4 replies Latest 8 days ago by mveereshm622 Answer this
Suggested answer AHB revisions from AHB3 to AHB5
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 0 votes 153 views 1 replies Latest 9 days ago by Colin Campbell Answer this
Suggested answer Burst termination with BUSY transfer on AHB
  • AMBA
  • AHB
 0 votes 131 views 1 replies Latest 9 days ago by Colin Campbell Answer this
Suggested answer Regarding retry response
  • AMBA
  • AHB
 0 votes 124 views 1 replies Latest 9 days ago by Colin Campbell Answer this
Not answered what action will be performed by the master based on the read and write responce in axi 4? Started 7 hours ago by Hem Patel 0 replies 20 views
Answered ACE protocol : Eviction and snoop request at same time Latest 8 days ago by Christopher Tory 1 replies 345 views
Suggested answer AXI3 write data interleaving with same AWID Latest 8 days ago by mveereshm622 4 replies 412 views
Suggested answer AHB revisions from AHB3 to AHB5 Latest 9 days ago by Colin Campbell 1 replies 153 views
Suggested answer Burst termination with BUSY transfer on AHB Latest 9 days ago by Colin Campbell 1 replies 131 views
Suggested answer Regarding retry response Latest 9 days ago by Colin Campbell 1 replies 124 views