The CoreSight ELA-600 Embedded Logic Analyzer inherits the debug capability and signal observability features of CoreSight ELA-500 with further optimization to improve data tracing efficiency and capacity. With CoreSight ELA-600, trigger condition can be set to initiate data tracing or output actions.
You also have the option of either storing trace data within CoreSight ELA-600 embedded SRAM in the same manner as CoreSight ELA-500 or aggregating them onto a larger memory area in the system/external to the SoC.
- Improve low-level signal observability and controllability in post-silicon debug.
- Shorten debug cycle by speeding up error root-cause analysis.
- Improve system efficiency with run-time signal monitoring and control.
CoreSight ELA-600 allows you to identify hard-to-diagnose bugs quickly. This accelerates silicon bring-up.
Start designing now
Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.
CoreSight ELA-500 and ELA-600 Comparison
CoreSight ELA-600 gives you additional enhancements that extend existing debug and trace use cases.
|Embedded RAM config|| ✔
|Data compression|| ✔
|Simultaneous trace of 2 SIGNALGRPs on same clock cycle||✔|
|Trigger state counters tracing||✔|
|32-bit segmented trigger state comparators||✔|
Technical Reference Manual
For system designers, systems integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.Read here
Useful documents and blogs for designing Arm-based SoCs:
Get support with Arm training courses and design reviews. You can also open a support case or manage existing cases.Arm training courses Arm Design Reviews Open a support case
|Suggested answer||strobe||0 votes||5326 views||3 replies||Latest 15 hours ago by Christopher Tory||Answer this|
|Not answered||BUSY transfer just before the last transfer in a burst by a AHB Master.||0 votes||214 views||0 replies||Started 23 hours ago by ISHWAR GANIGER||Answer this|
|Suggested answer||PADDR||0 votes||528 views||1 replies||Latest 2 days ago by Colin Campbell||Answer this|
|Not answered||ABP wrapper/ resizer 32-128 bit FPGA SoC||0 votes||471 views||0 replies||Started 6 days ago by Rann||Answer this|
|Answered||AXI4-Relationships between the channels||0 votes||782 views||1 replies||Latest 9 days ago by Colin Campbell||Answer this|
|Suggested answer||Semihosting 3.0||0 votes||1026 views||2 replies||Latest 9 days ago by koendv||Answer this|
|Suggested answer||strobe Latest 15 hours ago by Christopher Tory||3 replies 5326 views|
|Not answered||BUSY transfer just before the last transfer in a burst by a AHB Master. Started 23 hours ago by ISHWAR GANIGER||0 replies 214 views|
|Suggested answer||PADDR Latest 2 days ago by Colin Campbell||1 replies 528 views|
|Not answered||ABP wrapper/ resizer 32-128 bit FPGA SoC Started 6 days ago by Rann||0 replies 471 views|
|Answered||AXI4-Relationships between the channels Latest 9 days ago by Colin Campbell||1 replies 782 views|
|Suggested answer||Semihosting 3.0 Latest 9 days ago by koendv||2 replies 1026 views|