Arm CoreSight ELA-600 Embedded Logic Analyzer

CoreSight-ELA 600 Chip.

Getting Started

The CoreSight ELA-600 Embedded Logic Analyzer inherits the debug capability and signal observability features of CoreSight ELA-500 with further optimization to improve data tracing efficiency and capacity. With CoreSight ELA-600, trigger condition can be set to initiate data tracing or output actions.
You also have the option of either storing trace data within CoreSight ELA-600 embedded SRAM in the same manner as CoreSight ELA-500 or aggregating them onto a larger memory area in the system/external to the SoC. 

Benefits

  • Improve low-level signal observability and controllability in post-silicon debug.
  • Shorten debug cycle by speeding up error root-cause analysis.
  • Improve system efficiency with run-time signal monitoring and control.

Specifications

CoreSight ELA-600 allows you to identify hard-to-diagnose bugs quickly. This accelerates silicon bring-up.

ELA-600 schematic diagram showing 12 input group signals and main ELA-600 functions

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

Learn more

CoreSight ELA-500 and ELA-600 Comparison

CoreSight ELA-600 gives you additional enhancements that extend existing debug and trace use cases.

Feature ELA-500 ELA-600
Trigger states 5 8
Embedded RAM config  ✔
  ✔
Data compression    ✔
ATB interface    ✔
Simultaneous trace of 2 SIGNALGRPs on same clock cycle    ✔
Trigger state counters tracing    ✔
32-bit segmented trigger state comparators    ✔

  • Manual containing technical information.

  • Technical Reference Manual

    For system designers, systems integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Read here

Resources

Get support

Community Blogs

Blog post image
A painless upgrade to 22nm – the right cost with the available IP

In this blog, read about upgrading to 22nm in your ASIC design feature.

a month ago by Claudia Pike
Blog post image
Simplifying workload modeling with AMBA ATP Engine

Following the release of the AMBA Adaptive Traffic Profiles (ATP) Specification, we are pleased to announce the AMBA ATP Engine, to further facilitate ATP’s adoption into a variety of platforms.

4 months ago by Francisco Socal
1
Blog post image
Development of Arm based systems with Synopsys Virtual Prototyping:…

Find out more about virtual prototyping from Synopsys as thousands of engineers around the world have been asked to work from home.

4 months ago by Jason Andrews
Blog post image
Accelerating Innovation for Safety Systems with Arm Flexible Access

Arm is proud to announce the addition of Arm Safety Packages for select IP within Arm Flexible Access, with the goal to make it easier for developers in the automotive and other safety-related industries to create SoCs.

7 months ago by Chet Babla
Blog post image
Functional Safety on Arm – Beyond Automotive

Arm has moved a long way from the days where our only ‘safety’ requirement was to provide ECC or parity protections on CPU RAMs and we are now able to offer a number of System IP, GPUs, ISPs and NPUs as Safety Ready products. With Arm’s extensive…

9 months ago by Antonio Priore
1
Blog post image
Docker enables Arm Cycle Model Studio on Ubuntu

Arm Cycle Model Studio (CMS) is a great tool to create SystemC simulation models from Verilog RTL source code. This articles shows how to use Docker to run CMS and create models on an Ubuntu machine.

11 months ago by Jason Andrews
2

Community Forums

Not answered ICODE and DCODE Fetches
  • Cortex-M3
 0 votes 86 views 0 replies Started 2 days ago by eugch Answer this
Not answered Which ARM board will be most suitable?
  • Video Processor Embedded Algorithms
  • Video Processor
 0 votes 214 views 0 replies Started 2 days ago by Surya Answer this
Suggested answer test cases for apb 0 votes 339 views 3 replies Latest 3 days ago by Colin Campbell Answer this
Suggested answer what is different that change start address and use WSTRB signal for transfer 0 votes 253 views 1 replies Latest 3 days ago by Colin Campbell Answer this
Suggested answer why use unaligned transfers in AXI 0 votes 235 views 1 replies Latest 3 days ago by Colin Campbell Answer this
Suggested answer What purpose does SINGLE BURST feature in AHB serve? 0 votes 235 views 1 replies Latest 5 days ago by Colin Campbell Answer this
Not answered ICODE and DCODE Fetches Started 2 days ago by eugch 0 replies 86 views
Not answered Which ARM board will be most suitable? Started 2 days ago by Surya 0 replies 214 views
Suggested answer test cases for apb Latest 3 days ago by Colin Campbell 3 replies 339 views
Suggested answer what is different that change start address and use WSTRB signal for transfer Latest 3 days ago by Colin Campbell 1 replies 253 views
Suggested answer why use unaligned transfers in AXI Latest 3 days ago by Colin Campbell 1 replies 235 views
Suggested answer What purpose does SINGLE BURST feature in AHB serve? Latest 5 days ago by Colin Campbell 1 replies 235 views