The CoreSight ELA-600 Embedded Logic Analyzer inherits the debug capability and signal observability features of CoreSight ELA-500 with further optimization to improve data tracing efficiency and capacity. With CoreSight ELA-600, trigger condition can be set to initiate data tracing or output actions.
You also have the option of either storing trace data within CoreSight ELA-600 embedded SRAM in the same manner as CoreSight ELA-500 or aggregating them onto a larger memory area in the system/external to the SoC.
- Improve low-level signal observability and controllability in post-silicon debug.
- Shorten debug cycle by speeding up error root-cause analysis.
- Improve system efficiency with run-time signal monitoring and control.
CoreSight ELA-600 allows you to identify hard-to-diagnose bugs quickly. This accelerates silicon bring-up.
Start designing now
Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.
CoreSight ELA-500 and ELA-600 Comparison
CoreSight ELA-600 gives you additional enhancements that extend existing debug and trace use cases.
|Embedded RAM config|| ✔
|Data compression|| ✔
|Simultaneous trace of 2 SIGNALGRPs on same clock cycle||✔|
|Trigger state counters tracing||✔|
|32-bit segmented trigger state comparators||✔|
Technical Reference Manual
For system designers, systems integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.Read here
Useful documents and blogs for designing Arm-based SoCs:
Get support with Arm training courses and design reviews. You can also open a support case or manage existing cases.Arm training courses Arm Design Reviews Open a support case
|Answered||Forum FAQs||0 votes||3347 views||0 replies||Started 4 months ago by Annie||Answer this|
|Answered||Forum FAQs||0 votes||3260 views||0 replies||Started 4 months ago by Annie||Answer this|
|Suggested answer||Cortex M4 hard fault finding root cause on LPC4078 pc=0x0||0 votes||1307 views||15 replies||Latest 14 hours ago by tobermory||Answer this|
|Suggested answer||ARM Cortex ICode, DCode, System buses||0 votes||15337 views||9 replies||Latest 5 days ago by ele||Answer this|
|Not answered||How to know el1 is host kernel or guest kernel?||0 votes||59 views||0 replies||Started 5 days ago by dange||Answer this|
|Suggested answer||What is the correct data in BUSY state?||0 votes||1024 views||10 replies||Latest 6 days ago by Colin Campbell||Answer this|
|Answered||Forum FAQs Started 4 months ago by Annie||0 replies 3347 views|
|Answered||Forum FAQs Started 4 months ago by Annie||0 replies 3260 views|
|Suggested answer||Cortex M4 hard fault finding root cause on LPC4078 pc=0x0 Latest 14 hours ago by tobermory||15 replies 1307 views|
|Suggested answer||ARM Cortex ICode, DCode, System buses Latest 5 days ago by ele||9 replies 15337 views|
|Not answered||How to know el1 is host kernel or guest kernel? Started 5 days ago by dange||0 replies 59 views|
|Suggested answer||What is the correct data in BUSY state? Latest 6 days ago by Colin Campbell||10 replies 1024 views|