The CoreSight ELA-600 Embedded Logic Analyzer inherits the debug capability and signal observability features of CoreSight ELA-500 with further optimization to improve data tracing efficiency and capacity. With CoreSight ELA-600, trigger condition can be set to initiate data tracing or output actions.
You also have the option of either storing trace data within CoreSight ELA-600 embedded SRAM in the same manner as CoreSight ELA-500 or aggregating them onto a larger memory area in the system/external to the SoC.
- Improve low-level signal observability and controllability in post-silicon debug.
- Shorten debug cycle by speeding up error root-cause analysis.
- Improve system efficiency with run-time signal monitoring and control.
CoreSight ELA-600 allows you to identify hard-to-diagnose bugs quickly. This accelerates silicon bring-up.
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CoreSight ELA-500 and ELA-600 Comparison
CoreSight ELA-600 gives you additional enhancements that extend existing debug and trace use cases.
|Embedded RAM config|| ✔
|Data compression|| ✔
|Simultaneous trace of 2 SIGNALGRPs on same clock cycle||✔|
|Trigger state counters tracing||✔|
|32-bit segmented trigger state comparators||✔|
Technical Reference Manual
For system designers, systems integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.Read here
Useful documents and blogs for designing Arm-based SoCs:
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|Answered||Forum FAQs Started 1 months ago by Annie Cracknell||0 replies 2868 views|
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|Answered||ethernet sample code Latest yesterday by SRIDHAR R||9 replies 958 views|
|Not answered||APB - Purpose of PADDR? Started yesterday by Kyle Kochan||0 replies 50 views|
|Suggested answer||Need help to choose MCU Latest 3 days ago by Oliver Beirne||3 replies 666 views|
|Not answered||Does it use a Slow Clock to turn off Main Clock? Started 9 days ago by Ridge Mao||0 replies 94 views|