Arm CoreSight ELA-600 Embedded Logic Analyzer

CoreSight-ELA 600 Chip.

Getting Started

The CoreSight ELA-600 Embedded Logic Analyzer inherits the debug capability and signal observability features of CoreSight ELA-500 with further optimization to improve data tracing efficiency and capacity. With CoreSight ELA-600, trigger condition can be set to initiate data tracing or output actions.
You also have the option of either storing trace data within CoreSight ELA-600 embedded SRAM in the same manner as CoreSight ELA-500 or aggregating them onto a larger memory area in the system/external to the SoC. 

Benefits

  • Improve low-level signal observability and controllability in post-silicon debug.
  • Shorten debug cycle by speeding up error root-cause analysis.
  • Improve system efficiency with run-time signal monitoring and control.

Specifications

CoreSight ELA-600 allows you to identify hard-to-diagnose bugs quickly. This accelerates silicon bring-up.

ELA-600 schematic diagram showing 12 input group signals and main ELA-600 functions

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

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CoreSight ELA-500 and ELA-600 Comparison

CoreSight ELA-600 gives you additional enhancements that extend existing debug and trace use cases.

Feature ELA-500 ELA-600
Trigger states 5 8
Embedded RAM config  ✔
  ✔
Data compression    ✔
ATB interface    ✔
Simultaneous trace of 2 SIGNALGRPs on same clock cycle    ✔
Trigger state counters tracing    ✔
32-bit segmented trigger state comparators    ✔

  • Manual containing technical information.

  • Technical Reference Manual

    For system designers, systems integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Read here

Resources

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Suggested answer Hard fault handler problem - Cortex-M0+
  • R13 (SP Stack Pointer)
  • 3 (HardFault)
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Suggested answer After first execution control goes to task 2 but i want him to go to task1 what i suppose to do here?
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Suggested answer Is there any extra parameter needed to start networking on FVP_MPS2_M7 simulator?
  • Embedded Software
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Suggested answer Making ONVIF conformant surveillance camera with STM32H743.
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Suggested answer Which ARM board will be most suitable?
  • Video Processor Embedded Algorithms
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 0 votes 1931 views 3 replies Latest 7 days ago by Dharmalingam.K Answer this
Suggested answer Hard fault handler problem - Cortex-M0+ Latest 18 hours ago by Clonimus74 2 replies 800 views
Suggested answer After first execution control goes to task 2 but i want him to go to task1 what i suppose to do here? Latest 4 days ago by fixxxer 1 replies 454 views
Suggested answer Is there any extra parameter needed to start networking on FVP_MPS2_M7 simulator? Latest 4 days ago by fixxxer 1 replies 1158 views
Suggested answer L1 cache BW Latest 4 days ago by fixxxer 2 replies 582 views
Suggested answer Making ONVIF conformant surveillance camera with STM32H743. Latest 6 days ago by ibrahim1236 5 replies 1078 views
Suggested answer Which ARM board will be most suitable? Latest 7 days ago by Dharmalingam.K 3 replies 1931 views