The Arm CoreSight SDC-600 Secure Debug Channel

CoreSight SDC-600 Chip.

Getting Started

The Arm CoreSight SDC-600 Secure Debug Channel, provides a dedicated path to a debugged system for authenticating debug accesses. Key benefits include:

  • A standardized communication protocol
  • The first layer of protection against debug access attacks
  • Robust security solution with Arm Security IP

Specifications

Conventional Secure JTAG Controller CoreSight SDC-600
Need for external JTAG pins exposure Functional IO/JTAG pins
Simple key-based authentication Certificate and key-based authentication
No / lack of cryptographic involvement Fully interoperable with Crypto IP
Customized communication protocol Standard and open communication protocol

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

Key features

Authenticated debug through an always-on communication channel

CoreSight SDC-600 addresses the security needs of modern day devices, by allowing silicon and tool vendors to enforce protection and to police debug accesses into the system. This is achieved through a debug certificate, exchanged through a dedicated communication path of CoreSight SDC-600.

Complete end-to-end security solution

CoreSight SDC-600 is intended to work closely with Cryptographic elements, to provide a robust security solution through debug certificate authentication. Arm ensures that CoreSight SDC-600 is designed and tested, to work efficiently with Arm CoreSight IP and Arm Security IP. This provides the most reliable and predictable security implementation for authenticating debug accesses. 

Promoting efficient ecosystem adoption

CoreSight SDC-600 implements the Arm recommended communication protocol, which enables efficient handshake communication between an external agent and target system.

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0 votes 612 views 0 replies Started 9 days ago by Rann Answer this
Suggested answer AMBA AXI reset Latest yesterday by Ravi V. 2 replies 6794 views
Suggested answer optimize scaling that involves float division in M0 Latest yesterday by Broeker 2 replies 3090 views
Answered strobe Latest 3 days ago by Christopher Tory 3 replies 5513 views
Not answered BUSY transfer just before the last transfer in a burst by a AHB Master. Started 3 days ago by ISHWAR GANIGER 0 replies 355 views
Suggested answer PADDR Latest 5 days ago by Colin Campbell 1 replies 685 views
Not answered ABP wrapper/ resizer 32-128 bit FPGA SoC Started 9 days ago by Rann 0 replies 612 views