The Arm CoreSight SDC-600 Secure Debug Channel, provides a dedicated path to a debugged system for authenticating debug accesses. Key benefits include:
- A standardized communication protocol
- The first layer of protection against debug access attacks
- Robust security solution with Arm Security IP
|Conventional Secure JTAG Controller||CoreSight SDC-600|
|Need for external JTAG pins exposure||Functional IO/JTAG pins|
|Simple key-based authentication||Certificate and key-based authentication|
|No / lack of cryptographic involvement||Fully interoperable with Crypto IP|
|Customized communication protocol||Standard and open communication protocol|
Start designing now
Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.
Authenticated debug through an always-on communication channel
CoreSight SDC-600 addresses the security needs of modern day devices, by allowing silicon and tool vendors to enforce protection and to police debug accesses into the system. This is achieved through a debug certificate, exchanged through a dedicated communication path of CoreSight SDC-600.
Complete end-to-end security solution
CoreSight SDC-600 is intended to work closely with Cryptographic elements, to provide a robust security solution through debug certificate authentication. Arm ensures that CoreSight SDC-600 is designed and tested, to work efficiently with Arm CoreSight IP and Arm Security IP. This provides the most reliable and predictable security implementation for authenticating debug accesses.
Promoting efficient ecosystem adoption
CoreSight SDC-600 implements the Arm recommended communication protocol, which enables efficient handshake communication between an external agent and target system.
Get support with Arm training courses and design reviews. You can also open a support case or manage existing cases.Arm training courses Arm Design Reviews Open a support case
|Answered||Forum FAQs||0 votes||3347 views||0 replies||Started 4 months ago by Annie||Answer this|
|Answered||Forum FAQs||0 votes||3260 views||0 replies||Started 4 months ago by Annie||Answer this|
|Suggested answer||Cortex M4 hard fault finding root cause on LPC4078 pc=0x0||0 votes||1284 views||15 replies||Latest 5 hours ago by tobermory||Answer this|
|Suggested answer||ARM Cortex ICode, DCode, System buses||0 votes||15320 views||9 replies||Latest 5 days ago by ele||Answer this|
|Not answered||How to know el1 is host kernel or guest kernel?||0 votes||58 views||0 replies||Started 5 days ago by dange||Answer this|
|Suggested answer||What is the correct data in BUSY state?||0 votes||1021 views||10 replies||Latest 6 days ago by Colin Campbell||Answer this|
|Answered||Forum FAQs Started 4 months ago by Annie||0 replies 3347 views|
|Answered||Forum FAQs Started 4 months ago by Annie||0 replies 3260 views|
|Suggested answer||Cortex M4 hard fault finding root cause on LPC4078 pc=0x0 Latest 5 hours ago by tobermory||15 replies 1284 views|
|Suggested answer||ARM Cortex ICode, DCode, System buses Latest 5 days ago by ele||9 replies 15320 views|
|Not answered||How to know el1 is host kernel or guest kernel? Started 5 days ago by dange||0 replies 58 views|
|Suggested answer||What is the correct data in BUSY state? Latest 6 days ago by Colin Campbell||10 replies 1021 views|