The Arm CoreSight SDC-600 Secure Debug Channel, provides a dedicated path to a debugged system for authenticating debug accesses. Key benefits include:
- A standardized communication protocol
- The first layer of protection against debug access attacks
- Robust security solution with Arm Security IP
|Conventional Secure JTAG Controller||CoreSight SDC-600|
|Need for external JTAG pins exposure||Functional IO/JTAG pins|
|Simple key-based authentication||Certificate and key-based authentication|
|No / lack of cryptographic involvement||Fully interoperable with Crypto IP|
|Customized communication protocol||Standard and open communication protocol|
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Authenticated debug through an always-on communication channel
CoreSight SDC-600 addresses the security needs of modern day devices, by allowing silicon and tool vendors to enforce protection and to police debug accesses into the system. This is achieved through a debug certificate, exchanged through a dedicated communication path of CoreSight SDC-600.
Complete end-to-end security solution
CoreSight SDC-600 is intended to work closely with Cryptographic elements, to provide a robust security solution through debug certificate authentication. Arm ensures that CoreSight SDC-600 is designed and tested, to work efficiently with Arm CoreSight IP and Arm Security IP. This provides the most reliable and predictable security implementation for authenticating debug accesses.
Promoting efficient ecosystem adoption
CoreSight SDC-600 implements the Arm recommended communication protocol, which enables efficient handshake communication between an external agent and target system.
|Not answered||CHI protocol cache line states||0 votes||136 views||0 replies||Started 23 hours ago by S_Seth||Answer this|
|Not answered||STM32F769i-Discovery IP Camera Interface||0 votes||87 views||0 replies||Started yesterday by Kiran bhat||Answer this|
|Suggested answer||Store operations where the cache line is already cached (ACE protocol)||2 votes||6212 views||9 replies||Latest yesterday by het||Answer this|
|Not answered||Best most recent text on ARM arch||0 votes||185 views||0 replies||Started 4 days ago by d.ry||Answer this|
|Not answered||Readunique and cleanunique transactions in ACE protocol||0 votes||167 views||0 replies||Started 4 days ago by het||Answer this|
|Suggested answer||Raspberry pi 3 and .net 5 coreclr||1 votes||2079 views||2 replies||Latest 5 days ago by delinaty||Answer this|
|Not answered||CHI protocol cache line states Started 23 hours ago by S_Seth||0 replies 136 views|
|Not answered||STM32F769i-Discovery IP Camera Interface Started yesterday by Kiran bhat||0 replies 87 views|
|Suggested answer||Store operations where the cache line is already cached (ACE protocol) Latest yesterday by het||9 replies 6212 views|
|Not answered||Best most recent text on ARM arch Started 4 days ago by d.ry||0 replies 185 views|
|Not answered||Readunique and cleanunique transactions in ACE protocol Started 4 days ago by het||0 replies 167 views|
|Suggested answer||Raspberry pi 3 and .net 5 coreclr Latest 5 days ago by delinaty||2 replies 2079 views|