CoreSight SoC-400 

The Arm CoreSight SoC-400 is a comprehensive library of components for the creation of debug and trace functionality within a system.

CoreSight Soc-400 Chip.

Getting Started

The SoC-400 library offers configurable components to meet the exact requirements of your system, from small to multiprocessor Cortex-A class designs. With over 20 years of development behind it, CoreSight SoC-400 is the standard for Arm-based SoC designs and enjoys broad support from the tooling ecosystem.

  • Safeguard against costly delays.

  • The industry standard for debug and trace IP.

  • Comprehensive library of configurable on-chip debug and trace components.


  • Manual containing technical information.
  • CoreSight SoC-400 Technical Reference Manual

    For system designers, system integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Read here
  • A program that is running on a desktop.
  • Technical Introduction to CoreSight 

    Learn about the basics of Arm CoreSight debug and trace technology, and how to implement it in a system.

    Read here
  • A program that is running on a desktop.
  • Introduction to CoreSight SoC-400

    This short video introduces the motivation behind the requirement for debug and trace, and provides an overview of how CoreSight SoC-400 can help build this functionality into SoC designs.

    Watch video
  • A program that is running on a desktop.
  • Better trace for better software with Arm CoreSight

    This white paper explores the limitations of existing software debug and trace technologies, and explains how the Arm CoreSight System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, at the same time as applying existing open source trace infrastructures.

    Read here
  • A program that is running on a desktop.
  • Low pin-count debug interfaces for multi-device systems

    This white paper examines some alternatives to JTAG as a debug interface, and concludes that a Serial Wire Debug interface can be delivered with lower pin-count and higher performance, and at the same time, maintain support for multiprocessor systems and interoperability with test.

    Read here
  • Board that is the international standard.
  • Key steps to create a debug and trace solution for an Arm SoC

    The global cost of debugging software has risen to $312 billion annually. This whitepaper outlines the key steps to create a debug and trace solution for an Arm SoC.

    Read here

Resources

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Community Forums

Not answered what action will be performed by the master based on the read and write responce in axi 4?
  • AXI
  • AXI4
0 votes 16 views 0 replies Started 6 hours ago by Hem Patel Answer this
Answered ACE protocol : Eviction and snoop request at same time
  • AMBA
  • l1
  • ACE
  • cache
0 votes 344 views 1 replies Latest 8 days ago by Christopher Tory Answer this
Suggested answer AXI3 write data interleaving with same AWID
  • AMBA
  • AXI
0 votes 412 views 4 replies Latest 8 days ago by mveereshm622 Answer this
Suggested answer AHB revisions from AHB3 to AHB5
  • AMBA
  • AHB
0 votes 153 views 1 replies Latest 9 days ago by Colin Campbell Answer this
Suggested answer Burst termination with BUSY transfer on AHB
  • AMBA
  • AHB
0 votes 131 views 1 replies Latest 9 days ago by Colin Campbell Answer this
Suggested answer Regarding retry response
  • AMBA
  • AHB
0 votes 124 views 1 replies Latest 9 days ago by Colin Campbell Answer this
Not answered what action will be performed by the master based on the read and write responce in axi 4? Started 6 hours ago by Hem Patel 0 replies 16 views
Answered ACE protocol : Eviction and snoop request at same time Latest 8 days ago by Christopher Tory 1 replies 344 views
Suggested answer AXI3 write data interleaving with same AWID Latest 8 days ago by mveereshm622 4 replies 412 views
Suggested answer AHB revisions from AHB3 to AHB5 Latest 9 days ago by Colin Campbell 1 replies 153 views
Suggested answer Burst termination with BUSY transfer on AHB Latest 9 days ago by Colin Campbell 1 replies 131 views
Suggested answer Regarding retry response Latest 9 days ago by Colin Campbell 1 replies 124 views

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