CoreSight SoC-400 

The Arm CoreSight SoC-400 is a comprehensive library of components for the creation of debug and trace functionality within a system.

CoreSight Soc-400 Chip.

Getting Started

The SoC-400 library offers configurable components to meet the exact requirements of your system, from small to multiprocessor Cortex-A class designs. With over 20 years of development behind it, CoreSight SoC-400 is the standard for Arm-based SoC designs and enjoys broad support from the tooling ecosystem.

  • Safeguard against costly delays.
  • The industry standard for debug and trace IP.
  • Comprehensive library of configurable on-chip debug and trace components.
  • Start designing now

    Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.


    • Manual containing technical information.
    • CoreSight SoC-400 Technical Reference Manual

      For system designers, system integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

      Read here
    • A program that is running on a desktop.
    • Technical Introduction to CoreSight 

      Learn about the basics of Arm CoreSight debug and trace technology, and how to implement it in a system.

      Read here
    • A program that is running on a desktop.
    • Introduction to CoreSight SoC-400

      This short video introduces the motivation behind the requirement for debug and trace, and provides an overview of how CoreSight SoC-400 can help build this functionality into SoC designs.

      Watch video
    • A program that is running on a desktop.
    • Better trace for better software with Arm CoreSight

      This white paper explores the limitations of existing software debug and trace technologies, and explains how the Arm CoreSight System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, at the same time as applying existing open source trace infrastructures.

      Read here
    • A program that is running on a desktop.
    • Low pin-count debug interfaces for multi-device systems

      This white paper examines some alternatives to JTAG as a debug interface, and concludes that a Serial Wire Debug interface can be delivered with lower pin-count and higher performance, and at the same time, maintain support for multiprocessor systems and interoperability with test.

      Read here
    • Board that is the international standard.
    • Key steps to create a debug and trace solution for an Arm SoC

      The global cost of debugging software has risen to $312 billion annually. This whitepaper outlines the key steps to create a debug and trace solution for an Arm SoC.

      Read here

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    Suggested answer BUSY transfer and WAIT state both are using the same time ,How to perform the AHB?
    • AHB
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    Answered Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior
    • AMBA
    • ACE
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    0 votes 6837 views 6 replies Latest yesterday by AlexR Answer this
    Suggested answer AXI3 locked access
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    Answered Difference btw AXI3 and AXI4
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    0 votes 11036 views 6 replies Latest 2 days ago by Colin Campbell Answer this
    Answered WID not present in AXI4 0 votes 333 views 1 replies Latest 2 days ago by Colin Campbell Answer this
    Not answered 7 inch TFT image not good for sample code 0 votes 409 views 0 replies Started 2 days ago by sridhar6994 Answer this
    Suggested answer BUSY transfer and WAIT state both are using the same time ,How to perform the AHB? Latest yesterday by Mukul_Prajapati 2 replies 3590 views
    Answered Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior Latest yesterday by AlexR 6 replies 6837 views
    Suggested answer AXI3 locked access Latest 2 days ago by Colin Campbell 3 replies 3085 views
    Answered Difference btw AXI3 and AXI4 Latest 2 days ago by Colin Campbell 6 replies 11036 views
    Answered WID not present in AXI4 Latest 2 days ago by Colin Campbell 1 replies 333 views
    Not answered 7 inch TFT image not good for sample code Started 2 days ago by sridhar6994 0 replies 409 views

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