CoreSight SoC-400 

The Arm CoreSight SoC-400 is a comprehensive library of components for the creation of debug and trace functionality within a system.

CoreSight Soc-400 Chip.

Getting Started

The SoC-400 library offers configurable components to meet the exact requirements of your system, from small to multiprocessor Cortex-A class designs. With over 20 years of development behind it, CoreSight SoC-400 is the standard for Arm-based SoC designs and enjoys broad support from the tooling ecosystem.

  • Safeguard against costly delays.
  • The industry standard for debug and trace IP.
  • Comprehensive library of configurable on-chip debug and trace components.
  • Start designing now

    Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.


    • Manual containing technical information.
    • CoreSight SoC-400 Technical Reference Manual

      For system designers, system integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

      Read here
    • A program that is running on a desktop.
    • Technical Introduction to CoreSight 

      Learn about the basics of Arm CoreSight debug and trace technology, and how to implement it in a system.

      Read here
    • A program that is running on a desktop.
    • Introduction to CoreSight SoC-400

      This short video introduces the motivation behind the requirement for debug and trace, and provides an overview of how CoreSight SoC-400 can help build this functionality into SoC designs.

      Watch video
    • A program that is running on a desktop.
    • Better trace for better software with Arm CoreSight

      This white paper explores the limitations of existing software debug and trace technologies, and explains how the Arm CoreSight System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, at the same time as applying existing open source trace infrastructures.

      Read here
    • A program that is running on a desktop.
    • Low pin-count debug interfaces for multi-device systems

      This white paper examines some alternatives to JTAG as a debug interface, and concludes that a Serial Wire Debug interface can be delivered with lower pin-count and higher performance, and at the same time, maintain support for multiprocessor systems and interoperability with test.

      Read here
    • Board that is the international standard.
    • Key steps to create a debug and trace solution for an Arm SoC

      The global cost of debugging software has risen to $312 billion annually. This whitepaper outlines the key steps to create a debug and trace solution for an Arm SoC.

      Read here

    Resources

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    Not answered AXI fixed burst to a slave with narrow data width
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    0 votes 11 views 0 replies Started yesterday by Sana Answer this
    Suggested answer NOR, SPI, U-Boot, Kernal 0 votes 70 views 2 replies Latest yesterday by Andy Neil Answer this
    Answered Regarding implementation of a scenario in AHB protocol 0 votes 120 views 4 replies Latest 2 days ago by Suyash Sharma Answer this
    Suggested answer How could CMN600 route snoop transactions to RN-F 0 votes 316 views 2 replies Latest 3 days ago by Joe Chen Answer this
    Suggested answer Application scenarios of APB4 0 votes 331 views 1 replies Latest 4 days ago by Christopher Tory Answer this
    Suggested answer Outstanding support in AXI slave 0 votes 277 views 1 replies Latest 4 days ago by Christopher Tory Answer this
    Not answered AXI fixed burst to a slave with narrow data width Started yesterday by Sana 0 replies 11 views
    Suggested answer NOR, SPI, U-Boot, Kernal Latest yesterday by Andy Neil 2 replies 70 views
    Answered Regarding implementation of a scenario in AHB protocol Latest 2 days ago by Suyash Sharma 4 replies 120 views
    Suggested answer How could CMN600 route snoop transactions to RN-F Latest 3 days ago by Joe Chen 2 replies 316 views
    Suggested answer Application scenarios of APB4 Latest 4 days ago by Christopher Tory 1 replies 331 views
    Suggested answer Outstanding support in AXI slave Latest 4 days ago by Christopher Tory 1 replies 277 views