The SoC-400 library offers configurable components to meet the exact requirements of your system, from small to multiprocessor Cortex-A class designs. With over 20 years of development behind it, CoreSight SoC-400 is the standard for Arm-based SoC designs and enjoys broad support from the tooling ecosystem.
Safeguard against costly delays.
The industry standard for debug and trace IP.
Comprehensive library of configurable on-chip debug and trace components.
CoreSight SoC-400 Technical Reference Manual
For system designers, system integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.Read here
Technical Introduction to CoreSight
Learn about the basics of Arm CoreSight debug and trace technology, and how to implement it in a system.Read here
Introduction to CoreSight SoC-400
This short video introduces the motivation behind the requirement for debug and trace, and provides an overview of how CoreSight SoC-400 can help build this functionality into SoC designs.Watch video
Better trace for better software with Arm CoreSight
This white paper explores the limitations of existing software debug and trace technologies, and explains how the Arm CoreSight System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, at the same time as applying existing open source trace infrastructures.Read here
Low pin-count debug interfaces for multi-device systems
This white paper examines some alternatives to JTAG as a debug interface, and concludes that a Serial Wire Debug interface can be delivered with lower pin-count and higher performance, and at the same time, maintain support for multiprocessor systems and interoperability with test.Read here
Key steps to create a debug and trace solution for an Arm SoC
The global cost of debugging software has risen to $312 billion annually. This whitepaper outlines the key steps to create a debug and trace solution for an Arm SoC.Read here
Documents and blogs that are useful when designing Arm-based SoCs.
|Answered||what action will be performed by the master based on the read and write responce in axi 4?||0 votes||83 views||1 replies||Latest 2 days ago by Colin Campbell||Answer this|
|Answered||ACE protocol : Eviction and snoop request at same time||0 votes||375 views||1 replies||Latest 10 days ago by Christopher Tory||Answer this|
|Suggested answer||AXI3 write data interleaving with same AWID||0 votes||436 views||4 replies||Latest 11 days ago by mveereshm622||Answer this|
|Suggested answer||AHB revisions from AHB3 to AHB5||0 votes||167 views||1 replies||Latest 12 days ago by Colin Campbell||Answer this|
|Suggested answer||Burst termination with BUSY transfer on AHB||0 votes||151 views||1 replies||Latest 12 days ago by Colin Campbell||Answer this|
|Suggested answer||Regarding retry response||0 votes||139 views||1 replies||Latest 12 days ago by Colin Campbell||Answer this|
|Answered||what action will be performed by the master based on the read and write responce in axi 4? Latest 2 days ago by Colin Campbell||1 replies 83 views|
|Answered||ACE protocol : Eviction and snoop request at same time Latest 10 days ago by Christopher Tory||1 replies 375 views|
|Suggested answer||AXI3 write data interleaving with same AWID Latest 11 days ago by mveereshm622||4 replies 436 views|
|Suggested answer||AHB revisions from AHB3 to AHB5 Latest 12 days ago by Colin Campbell||1 replies 167 views|
|Suggested answer||Burst termination with BUSY transfer on AHB Latest 12 days ago by Colin Campbell||1 replies 151 views|
|Suggested answer||Regarding retry response Latest 12 days ago by Colin Campbell||1 replies 139 views|