CoreSight SoC-400 

The Arm CoreSight SoC-400 is a comprehensive library of components for the creation of debug and trace functionality within a system.

CoreSight Soc-400 Chip.

Getting Started

The SoC-400 library offers configurable components to meet the exact requirements of your system, from small to multiprocessor Cortex-A class designs. With over 20 years of development behind it, CoreSight SoC-400 is the standard for Arm-based SoC designs and enjoys broad support from the tooling ecosystem.

  • Safeguard against costly delays.
  • The industry standard for debug and trace IP.
  • Comprehensive library of configurable on-chip debug and trace components.
  • Start designing now

    Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.


    • Manual containing technical information.
    • CoreSight SoC-400 Technical Reference Manual

      For system designers, system integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

      Read here
    • A program that is running on a desktop.
    • Technical Introduction to CoreSight 

      Learn about the basics of Arm CoreSight debug and trace technology, and how to implement it in a system.

      Read here
    • A program that is running on a desktop.
    • Introduction to CoreSight SoC-400

      This short video introduces the motivation behind the requirement for debug and trace, and provides an overview of how CoreSight SoC-400 can help build this functionality into SoC designs.

      Watch video
    • A program that is running on a desktop.
    • Better trace for better software with Arm CoreSight

      This white paper explores the limitations of existing software debug and trace technologies, and explains how the Arm CoreSight System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, at the same time as applying existing open source trace infrastructures.

      Read here
    • A program that is running on a desktop.
    • Low pin-count debug interfaces for multi-device systems

      This white paper examines some alternatives to JTAG as a debug interface, and concludes that a Serial Wire Debug interface can be delivered with lower pin-count and higher performance, and at the same time, maintain support for multiprocessor systems and interoperability with test.

      Read here
    • Board that is the international standard.
    • Key steps to create a debug and trace solution for an Arm SoC

      The global cost of debugging software has risen to $312 billion annually. This whitepaper outlines the key steps to create a debug and trace solution for an Arm SoC.

      Read here

    Resources

    Get support

    Community Forums

    Not answered In APB, Why do we use enable signal? (Don't care about PREADY) 0 votes 35 views 0 replies Started yesterday by INNS Answer this
    Suggested answer DC/DC Controller SoC 0 votes 475 views 1 replies Latest 4 days ago by Andy Neil Answer this
    Suggested answer AMBA 5 CHI : Does Interleaving of TxnID within a Multiple flits message allowed?
    • System on Chip (SoC)
    • AMBA 5 CHI
    • CHI
    • Cache Architecture
    0 votes 610 views 1 replies Latest 7 days ago by IPDeveloper Answer this
    Answered ARM vs Thumb vs Thumb2 instruction set
    • T32 (Thumb)
    0 votes 9108 views 2 replies Latest 9 days ago by Kevin B Answer this
    Answered ARM/THUMB instructions that change execution path?
    • Thumb
    0 votes 62005 views 77 replies Latest 10 days ago by jakebunt Answer this
    Not answered ACE-Lite 0 votes 412 views 0 replies Started 10 days ago by Ishan Answer this
    Not answered In APB, Why do we use enable signal? (Don't care about PREADY) Started yesterday by INNS 0 replies 35 views
    Suggested answer DC/DC Controller SoC Latest 4 days ago by Andy Neil 1 replies 475 views
    Suggested answer AMBA 5 CHI : Does Interleaving of TxnID within a Multiple flits message allowed? Latest 7 days ago by IPDeveloper 1 replies 610 views
    Answered ARM vs Thumb vs Thumb2 instruction set Latest 9 days ago by Kevin B 2 replies 9108 views
    Answered ARM/THUMB instructions that change execution path? Latest 10 days ago by jakebunt 77 replies 62005 views
    Not answered ACE-Lite Started 10 days ago by Ishan 0 replies 412 views

    Community Blogs