Specifications

CoreSight SoC-600M is a library of debug and trace components for multi-core systems. The solution is optimized for Arm Cortex-M based devices. 

Benefits
  • Increased system visibility due to additional data bandwidth, reducing risks and increasing developer productivity
  • Remote debug and in-field access via Ethernet or wirelessly, reducing the total cost of ownership
  • Based on the proven Arm CoreSight SoC family used in millions of devices today
Features
  • Efficiently transports debug and trace data from multiple sources to external ports 
  • Enables debug and trace over functional interfaces such as WiFi, USB and Bluetooth in addition to widely used JTAG and SWD interfaces 
  • Provides debug access for starting/halting the debug or registering read/write 
  • Execution and instrumentation trace routing and termination 
  • Cross-triggering to coordinate debug and trace events such as the debug halt request 
  • Time stamping required for correlating traces from different sources 

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you are ready to manufacture.

Learn more

More than an IP library

CoreSight SoC-600M includes a number of components that support the development of secure and efficient SoCs. The following items have been developed alongside the IP library. 

Security

Debug access extended to functional IO needs to maintain the same level of security as offered through a JTAG connection.

Open-source Linux Drivers

Open-source Linux drivers are critical to self-hosted debug and these drivers will be supplied.

Tools and Software

CoreSight SoC-600M based SoCs will benefit from tools support in Arm Development Studio, as well as support from tool and software providers in the Arm ecosystem.

  • Manual containing technical information.

  • CoreSight SoC-600M Technical Reference Manual

    For system designers, system integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Read here
Training

Arm training is written and delivered by the world's most experienced Arm technology trainers. Arm also supports a network of third-party training providers who are licensed to deliver a number of related training courses. 

The top half of a human.

Designing with CoreSight

This course is intended for engineers designing silicon devices for Arm processors with the CoreSight debug architecture. The course covers an introduction to CoreSight and then presents detailed material on each aspect of the technology.

Learn more
Related IP

Hardware, software and tools that support the development of SoCs.

 Processor and System IP Tools and evaluation support  Software

Get Support

Community Blogs

Blog post image
Introducing Industry's-First 28FDS eMRAM IoT Test Chip and Board

The use of IoT devices is accelerating at a rapid pace, driven by the ongoing digital transformation. With the prediction of a trillion connected devices by 2035 and the growth of the big data, security and energy efficiency become the most demanding

1 years ago by Phil Morris
Blog post image
Arm CoreSight ELA-600 - the next generation of Embedded Logic Analyzer

Arm CoreSight ELA-600 is the next generation Embedded Logic Analyzer that extends the functionality of ELA-500 by including an external trace data output interface, this interface implements the AMBA Trace Bus (ATB) protocol.

2 years ago by Lip-Min Khor
Blog post image
Using the CoreSight ELA-500 Embedded Logic Analyzer with Arm DS-5

This guide is intended to demonstrate how the CoreSight ELA-500 can be used with Arm DS-5 Development Studio to debug a real-world deadlock scenario on a Cortex-A72 + CoreSight ELA-500 based system, caused by a bus transaction hang.

2 years ago by Luke Dare
Blog post image
New Arm CoreSight SDC-600 for secure, authenticated debug

The CoreSight SDC-600 Debug Authentication Channel provides a path into the security enclave, enforcing a secure API for communication between the external agent and the security enclave.

2 years ago by Lip-Min Khor
Blog post image
Trace capture/decode with CoreSight driver and Perf on Linux

Linaro support a solution for trace without external debugger involved. I take a test on Juno-busybox.

2 years ago by Kaiyou Wang
2
Blog post image
Arm-powered Xiaomi Mi 5c smartphone features the entire Arm Mali Multimedia…

Xiaomi recently launched the Mi 5c smartphone based on their Surge S1 SoC, incorporating more elements of Arm IP than any previous device.

3 years ago by Freddi Jeffries

Forums

Suggested answer AHB-lite Slave Burst Operation
  • AHB-Lite
 0 votes 266 views 2 replies Latest 14 hours ago by eugch Answer this
Not answered How to test L1/L2 cache? 0 votes 95 views 0 replies Started 16 hours ago by Zhiping Jiang Answer this
Not answered V2C-DAPLINK-035A shield schematic
  • FPGA
  • Debug Adapters
 0 votes 34 views 0 replies Started 18 hours ago by Brix Answer this
Answered Speculative execution/loads on Cortex-A5
  • Cortex-A5
  • Pipeline Control and Execution
  • Cache
 0 votes 1220 views 5 replies Latest 23 hours ago by vstehle Answer this
Suggested answer AHB-lite Slave Burst Operation Latest 14 hours ago by eugch 2 replies 266 views
Not answered How to test L1/L2 cache? Started 16 hours ago by Zhiping Jiang 0 replies 95 views
Not answered V2C-DAPLINK-035A shield schematic Started 18 hours ago by Brix 0 replies 34 views
Answered Speculative execution/loads on Cortex-A5 Latest 23 hours ago by vstehle 5 replies 1220 views