CoreSight SoC-600M is a library of debug and trace components for multi-core systems. The solution is optimized for Arm Cortex-M based devices. 

  • Increased system visibility due to additional data bandwidth, reducing risks and increasing developer productivity
  • Remote debug and in-field access via Ethernet or wirelessly, reducing the total cost of ownership
  • Based on the proven Arm CoreSight SoC family used in millions of devices today
  • Efficiently transports debug and trace data from multiple sources to external ports 
  • Enables debug and trace over functional interfaces such as WiFi, USB and Bluetooth in addition to widely used JTAG and SWD interfaces 
  • Provides debug access for starting/halting the debug or registering read/write 
  • Execution and instrumentation trace routing and termination 
  • Cross-triggering to coordinate debug and trace events such as the debug halt request 
  • Time stamping required for correlating traces from different sources 

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you are ready to manufacture.

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More than an IP library

CoreSight SoC-600M includes a number of components that support the development of secure and efficient SoCs. The following items have been developed alongside the IP library. 


Debug access extended to functional IO needs to maintain the same level of security as offered through a JTAG connection.

Open-source Linux Drivers

Open-source Linux drivers are critical to self-hosted debug and these drivers will be supplied.

Tools and Software

CoreSight SoC-600M based SoCs will benefit from tools support in Arm Development Studio, as well as support from tool and software providers in the Arm ecosystem.


Arm training is written and delivered by the world's most experienced Arm technology trainers. Arm also supports a network of third-party training providers who are licensed to deliver a number of related training courses. 

The top half of a human.

Designing with CoreSight

This course is intended for engineers designing silicon devices for Arm processors with the CoreSight debug architecture. The course covers an introduction to CoreSight and then presents detailed material on each aspect of the technology.

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Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A35 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

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Community Blogs

Suggested answer Audio Using LPC1768 (Cortex M3) 0 votes 382 views 2 replies Latest 11 hours ago by Raul77 Answer this
Not answered Bare Metal UART - Need Help 0 votes 52 views 0 replies Started 13 hours ago by Learner007 Answer this
Answered obtaining cycle count on cortex m7 0 votes 418 views 3 replies Latest 16 hours ago by 42Bastian Schick Answer this
Answered M4 Deep Sleep
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0 votes 405 views 2 replies Latest yesterday by AliRizaDenenPezevenk Answer this
Suggested answer Audio Using LPC1768 (Cortex M3) Latest 11 hours ago by Raul77 2 replies 382 views
Not answered Bare Metal UART - Need Help Started 13 hours ago by Learner007 0 replies 52 views
Answered obtaining cycle count on cortex m7 Latest 16 hours ago by 42Bastian Schick 3 replies 418 views
Answered M4 Deep Sleep Latest yesterday by AliRizaDenenPezevenk 2 replies 405 views