CoreSight STM-500

CoreSigh STM-500 Chip.

Getting Started

The STM-500 is a trace source that is integrated into a CoreSight system. CoreSight STM-500 is designed for high-bandwidth trace of instrumentation embedded into software. STM Advanced eXtensible Interface (AXI) slave is made up of memory-mapped writes, which carry information about the behavior of the software.

CoreSight STM-500 is a natural successor to the CoreSight Instrumentation Trace Macrocell (ITM) in mid- to high-performance applications.


CoreSight STM-500 Features

CoreSight STM-500 has the following features:

  • A fully synchronous design with one clock and two resets
  • One 64-bit AXI slave interface for extended stimulus port inputs
  • One hardware event observation interface for tracing 64 hardware events
  • One 32-bit debug APB slave interface for configuration and status
  • One 64-bit ATB slave interface for configuration and status
  • One DMA peripheral request interface that is compatible with the AMBA DMA Controller DMA-330
  • Two depth-configurable FIFO buffers for usage-optimized configurability:
    • Data FIFO
    • Channel information FIFO
  • A fully memory-mapped software stimulus supporting 65,536 stimulus ports and 128 masters
  • Leading zero data compression
  • Full support for guaranteed and invariant timing software stimulus writes
  • Support for single-shot and multi-shot triggers with a cross-trigger port, trigger packet insertion, and ATB trace triggers
  • An internal and an external source for STPv2 synchronization
  • Timestamping of trace events
  • Two low-power interfaces

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

  • A line drawing of a book.
  • CoreSight STM-500 Technical Reference Manual

     

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CoreSight STM-500 Community Blogs

CoreSight STM-500 Community Forums

Answered Debugging a Cortex-M0 Hard Fault
  • Armv6
  • Cortex-M0
  • Armv6-M
  • Armv7-M
  • Cortex-M3
  • Cortex-M
  • Debugging
0 votes 37759 views 6 replies Latest 26 days ago by delinaty Answer this
Answered I am working on protocol checker VC of APB4 to which I have to test the assertions written. Does it mean I have to write test cases to verify my assertions? 0 votes 2450 views 1 replies Latest 1 months ago by aditya raja Answer this
Answered Atomic access LDR/STR vs LDREX/STREX
  • AHB-Lite
  • DesignStart
0 votes 3213 views 2 replies Latest 1 months ago by EBB Answer this
Answered WSTRB calculation 0 votes 2991 views 2 replies Latest 2 months ago by Ravi V. Answer this
Answered Handshaking for the write data channel 0 votes 3307 views 3 replies Latest 2 months ago by Colin Campbell Answer this
Answered 7 inch TFT image not good for sample code 0 votes 3783 views 1 replies Latest 2 months ago by sridhar6994 Answer this
Answered Debugging a Cortex-M0 Hard Fault Latest 26 days ago by delinaty 6 replies 37759 views
Answered I am working on protocol checker VC of APB4 to which I have to test the assertions written. Does it mean I have to write test cases to verify my assertions? Latest 1 months ago by aditya raja 1 replies 2450 views
Answered Atomic access LDR/STR vs LDREX/STREX Latest 1 months ago by EBB 2 replies 3213 views
Answered WSTRB calculation Latest 2 months ago by Ravi V. 2 replies 2991 views
Answered Handshaking for the write data channel Latest 2 months ago by Colin Campbell 3 replies 3307 views
Answered 7 inch TFT image not good for sample code Latest 2 months ago by sridhar6994 1 replies 3783 views