CoreSight STM-500

CoreSigh STM-500 Chip.

Getting Started

The STM-500 is a trace source that is integrated into a CoreSight system. CoreSight STM-500 is designed for high-bandwidth trace of instrumentation embedded into software. STM Advanced eXtensible Interface (AXI) slave is made up of memory-mapped writes, which carry information about the behavior of the software.

CoreSight STM-500 is a natural successor to the CoreSight Instrumentation Trace Macrocell (ITM) in mid- to high-performance applications.


CoreSight STM-500 Features

CoreSight STM-500 has the following features:

  • A fully synchronous design with one clock and two resets
  • One 64-bit AXI slave interface for extended stimulus port inputs
  • One hardware event observation interface for tracing 64 hardware events
  • One 32-bit debug APB slave interface for configuration and status
  • One 64-bit ATB slave interface for configuration and status
  • One DMA peripheral request interface that is compatible with the AMBA DMA Controller DMA-330
  • Two depth-configurable FIFO buffers for usage-optimized configurability:
    • Data FIFO
    • Channel information FIFO
  • A fully memory-mapped software stimulus supporting 65,536 stimulus ports and 128 masters
  • Leading zero data compression
  • Full support for guaranteed and invariant timing software stimulus writes
  • Support for single-shot and multi-shot triggers with a cross-trigger port, trigger packet insertion, and ATB trace triggers
  • An internal and an external source for STPv2 synchronization
  • Timestamping of trace events
  • Two low-power interfaces

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

  • A line drawing of a book.
  • CoreSight STM-500 Technical Reference Manual

     

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CoreSight STM-500 Community Forums

Answered One master to two slave transfer (back to back) behavior for address A (slave1) and address B (slave2) 0 votes 215 views 1 replies Latest 4 days ago by Colin Campbell Answer this
Answered Is __CC_ARM not defined in the MDK Eval Version?
  • Keil MDK
  • Keil MDK Lite Edition
0 votes 776 views 12 replies Latest 5 days ago by Grant B Answer this
Answered EMBEDDED C - Volatile qualifier does not matter in my interrupt routine
  • Cortex-M7
  • stm32 h7
0 votes 2030 views 4 replies Latest 6 days ago by Thomas M. Hamilton Answer this
Answered ARM::CMSIS 5.8.0 breaks __nop() and__disable_irq() ??
  • Keil MDK
  • STM32 F1
  • CMSIS
0 votes 708 views 3 replies Latest 13 days ago by Grant B Answer this
Answered What's the purpose for WACK and RACK for ACE and what's the relationship with WVALID and RVALID ?
  • AMBA
  • ACE
0 votes 7855 views 3 replies Latest 20 days ago by Christopher Tory Answer this
Answered PSLVERR is optional for APB Master?
  • AMBA 3 APB Interface
0 votes 1776 views 2 replies Latest 27 days ago by Krupesh Answer this
Answered One master to two slave transfer (back to back) behavior for address A (slave1) and address B (slave2) Latest 4 days ago by Colin Campbell 1 replies 215 views
Answered Is __CC_ARM not defined in the MDK Eval Version? Latest 5 days ago by Grant B 12 replies 776 views
Answered EMBEDDED C - Volatile qualifier does not matter in my interrupt routine Latest 6 days ago by Thomas M. Hamilton 4 replies 2030 views
Answered ARM::CMSIS 5.8.0 breaks __nop() and__disable_irq() ?? Latest 13 days ago by Grant B 3 replies 708 views
Answered What's the purpose for WACK and RACK for ACE and what's the relationship with WVALID and RVALID ? Latest 20 days ago by Christopher Tory 3 replies 7855 views
Answered PSLVERR is optional for APB Master? Latest 27 days ago by Krupesh 2 replies 1776 views