CoreSight STM-500

CoreSigh STM-500 Chip.

Getting Started

The STM-500 is a trace source that is integrated into a CoreSight system. CoreSight STM-500 is designed for high-bandwidth trace of instrumentation embedded into software. STM Advanced eXtensible Interface (AXI) slave is made up of memory-mapped writes, which carry information about the behavior of the software.

CoreSight STM-500 is a natural successor to the CoreSight Instrumentation Trace Macrocell (ITM) in mid- to high-performance applications.


CoreSight STM-500 Features

CoreSight STM-500 has the following features:

  • A fully synchronous design with one clock and two resets
  • One 64-bit AXI slave interface for extended stimulus port inputs
  • One hardware event observation interface for tracing 64 hardware events
  • One 32-bit debug APB slave interface for configuration and status
  • One 64-bit ATB slave interface for configuration and status
  • One DMA peripheral request interface that is compatible with the AMBA DMA Controller DMA-330
  • Two depth-configurable FIFO buffers for usage-optimized configurability:
    • Data FIFO
    • Channel information FIFO
  • A fully memory-mapped software stimulus supporting 65,536 stimulus ports and 128 masters
  • Leading zero data compression
  • Full support for guaranteed and invariant timing software stimulus writes
  • Support for single-shot and multi-shot triggers with a cross-trigger port, trigger packet insertion, and ATB trace triggers
  • An internal and an external source for STPv2 synchronization
  • Timestamping of trace events
  • Two low-power interfaces

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

  • A line drawing of a book.
  • CoreSight STM-500 Technical Reference Manual

     

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CoreSight STM-500 Community Blogs

CoreSight STM-500 Community Forums

Answered Access to AHB signals 0 votes 684 views 1 replies Latest 25 days ago by Colin Campbell Answer this
Answered To generate a FIQ from ARM GIC apart from setting GICC_CTLR.FIQEn what else needs to be configured?
  • Interrupt Handling
  • System Controllers
  • Generic Interrupt Controller
  • Interrupt
0 votes 3085 views 2 replies Latest 27 days ago by Soummya Mallick Answer this
Answered why the inter-core SGI interrupt cannot be trigged on GICv3 hardware
  • Generic Interrupt Controller (GIC)
0 votes 4426 views 9 replies Latest 1 months ago by MSK Answer this
Answered how to calculate unaligned address for APB? 0 votes 851 views 6 replies Latest 1 months ago by aditya raja Answer this
Answered why PSTRB signal in APB4 have four bits?
  • APB
  • AMBA
  • AMBA 4
0 votes 1603 views 4 replies Latest 1 months ago by Colin Campbell Answer this
Answered I have a question about the destination of HWRITE data signal. 0 votes 452 views 1 replies Latest 1 months ago by Colin Campbell Answer this
Answered Access to AHB signals Latest 25 days ago by Colin Campbell 1 replies 684 views
Answered To generate a FIQ from ARM GIC apart from setting GICC_CTLR.FIQEn what else needs to be configured? Latest 27 days ago by Soummya Mallick 2 replies 3085 views
Answered why the inter-core SGI interrupt cannot be trigged on GICv3 hardware Latest 1 months ago by MSK 9 replies 4426 views
Answered how to calculate unaligned address for APB? Latest 1 months ago by aditya raja 6 replies 851 views
Answered why PSTRB signal in APB4 have four bits? Latest 1 months ago by Colin Campbell 4 replies 1603 views
Answered I have a question about the destination of HWRITE data signal. Latest 1 months ago by Colin Campbell 1 replies 452 views