CoreSight STM-500

CoreSigh STM-500 Chip.

Getting Started

The STM-500 is a trace source that is integrated into a CoreSight system. CoreSight STM-500 is designed for high-bandwidth trace of instrumentation embedded into software. STM Advanced eXtensible Interface (AXI) slave is made up of memory-mapped writes, which carry information about the behavior of the software.

CoreSight STM-500 is a natural successor to the CoreSight Instrumentation Trace Macrocell (ITM) in mid- to high-performance applications.


CoreSight STM-500 Features

CoreSight STM-500 has the following features:

  • A fully synchronous design with one clock and two resets
  • One 64-bit AXI slave interface for extended stimulus port inputs
  • One hardware event observation interface for tracing 64 hardware events
  • One 32-bit debug APB slave interface for configuration and status
  • One 64-bit ATB slave interface for configuration and status
  • One DMA peripheral request interface that is compatible with the AMBA DMA Controller DMA-330
  • Two depth-configurable FIFO buffers for usage-optimized configurability:
    • Data FIFO
    • Channel information FIFO
  • A fully memory-mapped software stimulus supporting 65,536 stimulus ports and 128 masters
  • Leading zero data compression
  • Full support for guaranteed and invariant timing software stimulus writes
  • Support for single-shot and multi-shot triggers with a cross-trigger port, trigger packet insertion, and ATB trace triggers
  • An internal and an external source for STPv2 synchronization
  • Timestamping of trace events
  • Two low-power interfaces

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

  • A line drawing of a book.
  • CoreSight STM-500 Technical Reference Manual

     

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CoreSight STM-500 Community Forums

Answered Regarding implementation of a scenario in AHB protocol 0 votes 175 views 4 replies Latest 3 days ago by Suyash Sharma Answer this
Answered Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior
  • AMBA
  • ACE
  • ACE 5
  • interconnect
  • AMBA 5
0 votes 2939 views 5 replies Latest 6 days ago by Christopher Tory Answer this
Answered Difference btw AXI3 and AXI4
  • AMBA
  • AXI3
  • AXI4
  • Interface
0 votes 6012 views 4 replies Latest 9 days ago by amareshpc Answer this
Answered AXI4 ordering 0 votes 1964 views 6 replies Latest 16 days ago by Hyunkyu Answer this
Answered Different STM32F405RGxx MCUs
  • STM32 F4
0 votes 888 views 4 replies Latest 17 days ago by Andy Neil Answer this
Answered AHB Bus Protocol -- Address Phase
  • Address
  • AHB-Lite
0 votes 3000 views 9 replies Latest 19 days ago by eugch Answer this
Answered Regarding implementation of a scenario in AHB protocol Latest 3 days ago by Suyash Sharma 4 replies 175 views
Answered Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior Latest 6 days ago by Christopher Tory 5 replies 2939 views
Answered Difference btw AXI3 and AXI4 Latest 9 days ago by amareshpc 4 replies 6012 views
Answered AXI4 ordering Latest 16 days ago by Hyunkyu 6 replies 1964 views
Answered Different STM32F405RGxx MCUs Latest 17 days ago by Andy Neil 4 replies 888 views
Answered AHB Bus Protocol -- Address Phase Latest 19 days ago by eugch 9 replies 3000 views