CoreSight STM-500

CoreSigh STM-500 Chip.

Getting Started

The STM-500 is a trace source that is integrated into a CoreSight system. CoreSight STM-500 is designed for high-bandwidth trace of instrumentation embedded into software. STM Advanced eXtensible Interface (AXI) slave is made up of memory-mapped writes, which carry information about the behavior of the software.

CoreSight STM-500 is a natural successor to the CoreSight Instrumentation Trace Macrocell (ITM) in mid- to high-performance applications.


CoreSight STM-500 Features

CoreSight STM-500 has the following features:

  • A fully synchronous design with one clock and two resets
  • One 64-bit AXI slave interface for extended stimulus port inputs
  • One hardware event observation interface for tracing 64 hardware events
  • One 32-bit debug APB slave interface for configuration and status
  • One 64-bit ATB slave interface for configuration and status
  • One DMA peripheral request interface that is compatible with the AMBA DMA Controller DMA-330
  • Two depth-configurable FIFO buffers for usage-optimized configurability:
    • Data FIFO
    • Channel information FIFO
  • A fully memory-mapped software stimulus supporting 65,536 stimulus ports and 128 masters
  • Leading zero data compression
  • Full support for guaranteed and invariant timing software stimulus writes
  • Support for single-shot and multi-shot triggers with a cross-trigger port, trigger packet insertion, and ATB trace triggers
  • An internal and an external source for STPv2 synchronization
  • Timestamping of trace events
  • Two low-power interfaces

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

  • A line drawing of a book.
  • CoreSight STM-500 Technical Reference Manual

     

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CoreSight STM-500 Community Forums

Answered IP Camera interface via STM32
  • Cortex-M
  • STM32F
  • Cortex-M4
1 votes 36826 views 8 replies Latest 7 days ago by Akash Kasturi Answer this
Answered spi flash 16MB not working 1 votes 9473 views 2 replies Latest 18 days ago by sridhar6994 Answer this
Answered response ordering at AXI4 slave
  • AXI4
0 votes 2177 views 4 replies Latest 1 months ago by rvora Answer this
Answered Can AHB3_Lite master send an unaligend address?
  • AMBA 4
  • AXI4
  • AHB-Lite
0 votes 1713 views 2 replies Latest 1 months ago by Oliver Beirne Answer this
Answered AHB DeadLock: HREADY=0 & HTRANS=BUSY 0 votes 1820 views 3 replies Latest 1 months ago by Oliver Beirne Answer this
Discussion IDE Recommendation
  • Cortex-M3
  • IDEs and Tool Suites
  • Cortex-M
0 votes 7137 views 6 replies Latest 1 months ago by Andy Neil Answer this
Answered IP Camera interface via STM32 Latest 7 days ago by Akash Kasturi 8 replies 36826 views
Answered spi flash 16MB not working Latest 18 days ago by sridhar6994 2 replies 9473 views
Answered response ordering at AXI4 slave Latest 1 months ago by rvora 4 replies 2177 views
Answered Can AHB3_Lite master send an unaligend address? Latest 1 months ago by Oliver Beirne 2 replies 1713 views
Answered AHB DeadLock: HREADY=0 & HTRANS=BUSY Latest 1 months ago by Oliver Beirne 3 replies 1820 views
Discussion IDE Recommendation Latest 1 months ago by Andy Neil 6 replies 7137 views