CoreSight STM-500

CoreSigh STM-500 Chip.

Getting Started

The STM-500 is a trace source that is integrated into a CoreSight system. CoreSight STM-500 is designed for high-bandwidth trace of instrumentation embedded into software. STM Advanced eXtensible Interface (AXI) slave is made up of memory-mapped writes, which carry information about the behavior of the software.

CoreSight STM-500 is a natural successor to the CoreSight Instrumentation Trace Macrocell (ITM) in mid- to high-performance applications.


CoreSight STM-500 Features

CoreSight STM-500 has the following features:

  • A fully synchronous design with one clock and two resets
  • One 64-bit AXI slave interface for extended stimulus port inputs
  • One hardware event observation interface for tracing 64 hardware events
  • One 32-bit debug APB slave interface for configuration and status
  • One 64-bit ATB slave interface for configuration and status
  • One DMA peripheral request interface that is compatible with the AMBA DMA Controller DMA-330
  • Two depth-configurable FIFO buffers for usage-optimized configurability:
    • Data FIFO
    • Channel information FIFO
  • A fully memory-mapped software stimulus supporting 65,536 stimulus ports and 128 masters
  • Leading zero data compression
  • Full support for guaranteed and invariant timing software stimulus writes
  • Support for single-shot and multi-shot triggers with a cross-trigger port, trigger packet insertion, and ATB trace triggers
  • An internal and an external source for STPv2 synchronization
  • Timestamping of trace events
  • Two low-power interfaces

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

  • A line drawing of a book.
  • CoreSight STM-500 Technical Reference Manual

     

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CoreSight STM-500 Community Blogs

CoreSight STM-500 Community Forums

Answered arm9 family nuvoton 0 votes 738 views 1 replies Latest 4 days ago by sridhar6994 Answer this
Answered NUVOTON N9H 0 votes 1520 views 6 replies Latest 4 days ago by sridhar6994 Answer this
Answered FIXED WRITE transfer of AWLEN=8'd4 in AXI4 0 votes 336 views 1 replies Latest 6 days ago by Colin Campbell Answer this
Answered Handling invalid AXI address requests
  • AXI4-Lite
  • Cortex-M System Design Kit
  • Cortex-M
0 votes 663 views 1 replies Latest 6 days ago by Colin Campbell Answer this
Answered AXI INC type transfer 0 votes 671 views 2 replies Latest 6 days ago by Ravi V. Answer this
Answered Question about AXI4 WLAST 0 votes 1076 views 1 replies Latest 12 days ago by Colin Campbell Answer this
Answered arm9 family nuvoton Latest 4 days ago by sridhar6994 1 replies 738 views
Answered NUVOTON N9H Latest 4 days ago by sridhar6994 6 replies 1520 views
Answered FIXED WRITE transfer of AWLEN=8'd4 in AXI4 Latest 6 days ago by Colin Campbell 1 replies 336 views
Answered Handling invalid AXI address requests Latest 6 days ago by Colin Campbell 1 replies 663 views
Answered AXI INC type transfer Latest 6 days ago by Ravi V. 2 replies 671 views
Answered Question about AXI4 WLAST Latest 12 days ago by Colin Campbell 1 replies 1076 views