CoreSight STM-500

CoreSigh STM-500 Chip.

Getting Started

The STM-500 is a trace source that is integrated into a CoreSight system. CoreSight STM-500 is designed for high-bandwidth trace of instrumentation embedded into software. STM Advanced eXtensible Interface (AXI) slave is made up of memory-mapped writes, which carry information about the behavior of the software.

CoreSight STM-500 is a natural successor to the CoreSight Instrumentation Trace Macrocell (ITM) in mid- to high-performance applications.


CoreSight STM-500 Features

CoreSight STM-500 has the following features:

  • A fully synchronous design with one clock and two resets
  • One 64-bit AXI slave interface for extended stimulus port inputs
  • One hardware event observation interface for tracing 64 hardware events
  • One 32-bit debug APB slave interface for configuration and status
  • One 64-bit ATB slave interface for configuration and status
  • One DMA peripheral request interface that is compatible with the AMBA DMA Controller DMA-330
  • Two depth-configurable FIFO buffers for usage-optimized configurability:
    • Data FIFO
    • Channel information FIFO
  • A fully memory-mapped software stimulus supporting 65,536 stimulus ports and 128 masters
  • Leading zero data compression
  • Full support for guaranteed and invariant timing software stimulus writes
  • Support for single-shot and multi-shot triggers with a cross-trigger port, trigger packet insertion, and ATB trace triggers
  • An internal and an external source for STPv2 synchronization
  • Timestamping of trace events
  • Two low-power interfaces
  • A line drawing of a book.
  • CoreSight STM-500 Technical Reference Manual

     

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CoreSight STM-500 Community Blogs

CoreSight STM-500 Community Forums

Answered ACE protocol : Eviction and snoop request at same time
  • AMBA
  • l1
  • ACE
  • cache
0 votes 329 views 1 replies Latest 6 days ago by Christopher Tory Answer this
Answered Does AHB-Lite Protocol require the master processor to be pipelined?
  • ahb-lite
  • Processor Architecture
0 votes 149 views 1 replies Latest 13 days ago by Colin Campbell Answer this
Answered APB process when pstrb = "0000" or "0101" during write transaction 0 votes 249 views 2 replies Latest 18 days ago by Hyunkyu Answer this
Answered How do I add AHB interface to a processor with Load Store Architecture?
  • Processor Architecture
  • AMBA 2 AHB Interface
  • AHB
0 votes 407 views 2 replies Latest 23 days ago by Kedhar Guhan Answer this
Answered How to use SCB_DisableDCache() correctly? 0 votes 292 views 2 replies Latest 1 months ago by Shmuelg Answer this
Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?
  • AXI
0 votes 365 views 2 replies Latest 1 months ago by Zax Answer this
Answered ACE protocol : Eviction and snoop request at same time Latest 6 days ago by Christopher Tory 1 replies 329 views
Answered Does AHB-Lite Protocol require the master processor to be pipelined? Latest 13 days ago by Colin Campbell 1 replies 149 views
Answered APB process when pstrb = "0000" or "0101" during write transaction Latest 18 days ago by Hyunkyu 2 replies 249 views
Answered How do I add AHB interface to a processor with Load Store Architecture? Latest 23 days ago by Kedhar Guhan 2 replies 407 views
Answered How to use SCB_DisableDCache() correctly? Latest 1 months ago by Shmuelg 2 replies 292 views
Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst? Latest 1 months ago by Zax 2 replies 365 views