System Trace Macrocell

Getting Started

The Arm CoreSight System Trace Macrocell (STM) is a trace source that enables real-time instrumentation of software with no impact on system behavior or performance. For software, system and hardware engineers, visibility of the complete system is now critical. This is due to the need to deliver high performance, power optimized systems in shorter development cycles.

The Arm CoreSight System Trace Macrocell (STM) extends low-cost real-time visibility of software and hardware execution to all software developers. In particular application and kernel developers, enabling rich, optimized and low power software on Arm processor-powered devices across the whole supply chain.

CoreSight technical introduction

Learn about the basics of Arm CoreSight debug and trace technology, and how to implement it in a system.
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Introduction to CoreSight SoC-400

This short video introduces the motivation behind the requirement for debug and trace, and provides an overview of how CoreSight SoC-400 can help build this functionality into SoC designs.
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Better trace for better software with Arm CoreSight

This white paper explores the limitations of existing software debug and trace technologies, and explains how the Arm CoreSight System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, at the same time as applying existing open source trace infrastructures.
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Low pin-count debug interfaces for multi-device systems

This white paper examines some alternatives to JTAG as a debug interface, and concludes that a serial wire debug interface can be delivered with lower pin-count and higher performance, and maintain support for multiprocessor systems and interoperability with test.
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Key steps to create a debug and trace solution for an Arm SoC

The global cost of debugging software has risen to $312 billion annually. This whitepaper outlines the key steps to create a debug and trace solution for an Arm SoC.
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Community Forums

Answered	ACE protocol : Eviction and snoop request at same time AMBA l1 ACE cache	329 views	1 replies	Latest 6 days ago by Christopher Tory	Answer this
Suggested answer	AXI3 write data interleaving with same AWID AMBA AXI	392 views	4 replies	Latest 6 days ago by mveereshm622	Answer this
Suggested answer	AHB revisions from AHB3 to AHB5 AMBA AHB	143 views	1 replies	Latest 7 days ago by Colin Campbell	Answer this
Suggested answer	Burst termination with BUSY transfer on AHB AMBA AHB	125 views	1 replies	Latest 7 days ago by Colin Campbell	Answer this
Suggested answer	Regarding retry response AMBA AHB	116 views	1 replies	Latest 7 days ago by Colin Campbell	Answer this
Suggested answer	APB3 Slave responding when PSEL = 0 APB AMBA	320 views	2 replies	Latest 11 days ago by vshankar11	Answer this

Answered	ACE protocol : Eviction and snoop request at same time Latest 6 days ago by Christopher Tory	1 replies 329 views
Suggested answer	AXI3 write data interleaving with same AWID Latest 6 days ago by mveereshm622	4 replies 392 views
Suggested answer	AHB revisions from AHB3 to AHB5 Latest 7 days ago by Colin Campbell	1 replies 143 views
Suggested answer	Burst termination with BUSY transfer on AHB Latest 7 days ago by Colin Campbell	1 replies 125 views
Suggested answer	Regarding retry response Latest 7 days ago by Colin Campbell	1 replies 116 views
Suggested answer	APB3 Slave responding when PSEL = 0 Latest 11 days ago by vshankar11	2 replies 320 views