System Trace Macrocell

Getting Started

The Arm CoreSight System Trace Macrocell (STM) is a trace source that enables real-time instrumentation of software with no impact on system behavior or performance. For software, system and hardware engineers, visibility of the complete system is now critical. This is due to the need to deliver high performance, power optimized systems in shorter development cycles.

The Arm CoreSight System Trace Macrocell (STM) extends low-cost real-time visibility of software and hardware execution to all software developers. In particular application and kernel developers, enabling rich, optimized and low power software on Arm processor-powered devices across the whole supply chain.

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

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CoreSight technical introduction

Learn about the basics of Arm CoreSight debug and trace technology, and how to implement it in a system.
Read here
Introduction to CoreSight SoC-400

This short video introduces the motivation behind the requirement for debug and trace, and provides an overview of how CoreSight SoC-400 can help build this functionality into SoC designs.
Watch video
Better trace for better software with Arm CoreSight

This white paper explores the limitations of existing software debug and trace technologies, and explains how the Arm CoreSight System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, at the same time as applying existing open source trace infrastructures.
Read here
Low pin-count debug interfaces for multi-device systems

This white paper examines some alternatives to JTAG as a debug interface, and concludes that a serial wire debug interface can be delivered with lower pin-count and higher performance, and maintain support for multiprocessor systems and interoperability with test.
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Key steps to create a debug and trace solution for an Arm SoC

The global cost of debugging software has risen to $312 billion annually. This whitepaper outlines the key steps to create a debug and trace solution for an Arm SoC.
Read here

Community Blogs

Take the fast track to autonomy with software tools for Cortex-A78AE and Ma

In this blog, read about how to fast track development to autonomy with software tools for the latest Cortex-A78AE and Mali-G78AE IP.

yesterday by Ronan Synnott

Arm Cortex-A78AE: On the Road to an Autonomous Future

Arm's newest member of the AE family of CPUs, the Cortex-A78AE, comes just in time to service our partners’ ever-growing need for safe compute.

yesterday by Srikanth Rengarajan

Arm Mali-C71AE: High performance Image Signal Processing with Advanced Safe

Mali-C71AE will be Arm’s highest performance image signal processor (ISP) now with comprehensive safety capability.

yesterday by Graeme Voller

Mali-G78AE: Arm’s First High-Performance GPU with Functional Safety

Arm has brought to market its first high performance GPU with functional safety, Mali-G78AE.

yesterday by Jake Kochnowicz

A painless upgrade to 22nm – the right cost with the available IP

In this blog, read about upgrading to 22nm in your ASIC design feature.

1 months ago by Claudia Pike

Simplifying workload modeling with AMBA ATP Engine

Following the release of the AMBA Adaptive Traffic Profiles (ATP) Specification, we are pleased to announce the AMBA ATP Engine, to further facilitate ATP’s adoption into a variety of platforms.

4 months ago by Francisco Socal

Community Forums

Not answered	ICODE and DCODE Fetches Cortex-M3	375 views	0 replies	Started 5 days ago by eugch	Answer this
Not answered	Which ARM board will be most suitable? Video Processor Embedded Algorithms Video Processor	247 views	0 replies	Started 6 days ago by Surya	Answer this
Suggested answer	test cases for apb	620 views	3 replies	Latest 6 days ago by Colin Campbell	Answer this
Suggested answer	what is different that change start address and use WSTRB signal for transfer	445 views	1 replies	Latest 7 days ago by Colin Campbell	Answer this
Suggested answer	why use unaligned transfers in AXI	421 views	1 replies	Latest 7 days ago by Colin Campbell	Answer this
Suggested answer	What purpose does SINGLE BURST feature in AHB serve?	389 views	1 replies	Latest 9 days ago by Colin Campbell	Answer this

Not answered	ICODE and DCODE Fetches Started 5 days ago by eugch	0 replies 375 views
Not answered	Which ARM board will be most suitable? Started 6 days ago by Surya	0 replies 247 views
Suggested answer	test cases for apb Latest 6 days ago by Colin Campbell	3 replies 620 views
Suggested answer	what is different that change start address and use WSTRB signal for transfer Latest 7 days ago by Colin Campbell	1 replies 445 views
Suggested answer	why use unaligned transfers in AXI Latest 7 days ago by Colin Campbell	1 replies 421 views
Suggested answer	What purpose does SINGLE BURST feature in AHB serve? Latest 9 days ago by Colin Campbell	1 replies 389 views