System Trace Macrocell

Getting Started

The Arm CoreSight System Trace Macrocell (STM) is a trace source that enables real-time instrumentation of software with no impact on system behavior or performance. For software, system and hardware engineers, visibility of the complete system is now critical. This is due to the need to deliver high performance, power optimized systems in shorter development cycles.

The Arm CoreSight System Trace Macrocell (STM) extends low-cost real-time visibility of software and hardware execution to all software developers. In particular application and kernel developers, enabling rich, optimized and low power software on Arm processor-powered devices across the whole supply chain.

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.


  • A program that is running on a desktop.
  • CoreSight technical introduction

    Learn about the basics of Arm CoreSight debug and trace technology, and how to implement it in a system.

    Read here
  • A program that is running on a desktop.
  • Introduction to CoreSight SoC-400

    This short video introduces the motivation behind the requirement for debug and trace, and provides an overview of how CoreSight SoC-400 can help build this functionality into SoC designs.

    Watch video
  • A program that is running on a desktop.
  • Better trace for better software with Arm CoreSight

    This white paper explores the limitations of existing software debug and trace technologies, and explains how the Arm CoreSight System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, at the same time as applying existing open source trace infrastructures.

    Read here
  • A program that is running on a desktop.
  • Low pin-count debug interfaces for multi-device systems

    This white paper examines some alternatives to JTAG as a debug interface, and concludes that a serial wire debug interface can be delivered with lower pin-count and higher performance, and maintain support for multiprocessor systems and interoperability with test.

    Read here
  • A development Board.
  • Key steps to create a debug and trace solution for an Arm SoC

    The global cost of debugging software has risen to $312 billion annually. This whitepaper outlines the key steps to create a debug and trace solution for an Arm SoC.

    Read here

Resources

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Community Blogs

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Not answered WID not present in AXI4 0 votes 91 views 0 replies Started 14 hours ago by Ravi V. Answer this
Not answered Vacuum pump waste gas treatment equipment 0 votes 143 views 0 replies Started yesterday by lay1014 Answer this
Answered arm9 family nuvoton 0 votes 675 views 1 replies Latest yesterday by sridhar6994 Answer this
Answered NUVOTON N9H 0 votes 1419 views 6 replies Latest yesterday by sridhar6994 Answer this
Not answered How to get Interrupt number (IRQ number) during kernel panic in interrupt context?
  • CoreLink GIC-400 Generic Interrupt Controller
  • Interrupt Handling
0 votes 330 views 0 replies Started yesterday by Rajeshkumar Answer this
Answered FIXED WRITE transfer of AWLEN=8'd4 in AXI4 0 votes 300 views 1 replies Latest 3 days ago by Colin Campbell Answer this
Not answered WID not present in AXI4 Started 14 hours ago by Ravi V. 0 replies 91 views
Not answered Vacuum pump waste gas treatment equipment Started yesterday by lay1014 0 replies 143 views
Answered arm9 family nuvoton Latest yesterday by sridhar6994 1 replies 675 views
Answered NUVOTON N9H Latest yesterday by sridhar6994 6 replies 1419 views
Not answered How to get Interrupt number (IRQ number) during kernel panic in interrupt context? Started yesterday by Rajeshkumar 0 replies 330 views
Answered FIXED WRITE transfer of AWLEN=8'd4 in AXI4 Latest 3 days ago by Colin Campbell 1 replies 300 views