System Trace Macrocell

Getting Started

The Arm CoreSight System Trace Macrocell (STM) is a trace source that enables real-time instrumentation of software with no impact on system behavior or performance. For software, system and hardware engineers, visibility of the complete system is now critical. This is due to the need to deliver high performance, power optimized systems in shorter development cycles.

The Arm CoreSight System Trace Macrocell (STM) extends low-cost real-time visibility of software and hardware execution to all software developers. In particular application and kernel developers, enabling rich, optimized and low power software on Arm processor-powered devices across the whole supply chain.

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.


  • A program that is running on a desktop.
  • CoreSight technical introduction

    Learn about the basics of Arm CoreSight debug and trace technology, and how to implement it in a system.

    Read here
  • A program that is running on a desktop.
  • Introduction to CoreSight SoC-400

    This short video introduces the motivation behind the requirement for debug and trace, and provides an overview of how CoreSight SoC-400 can help build this functionality into SoC designs.

    Watch video
  • A program that is running on a desktop.
  • Better trace for better software with Arm CoreSight

    This white paper explores the limitations of existing software debug and trace technologies, and explains how the Arm CoreSight System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, at the same time as applying existing open source trace infrastructures.

    Read here
  • A program that is running on a desktop.
  • Low pin-count debug interfaces for multi-device systems

    This white paper examines some alternatives to JTAG as a debug interface, and concludes that a serial wire debug interface can be delivered with lower pin-count and higher performance, and maintain support for multiprocessor systems and interoperability with test.

    Read here
  • A development Board.
  • Key steps to create a debug and trace solution for an Arm SoC

    The global cost of debugging software has risen to $312 billion annually. This whitepaper outlines the key steps to create a debug and trace solution for an Arm SoC.

    Read here

Resources

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Get support

Community Blogs

Community Forums

Not answered CHI protocol cache line states
  • AMBA 5 CHI
  • SoC Verification
0 votes 136 views 0 replies Started 23 hours ago by S_Seth Answer this
Not answered STM32F769i-Discovery IP Camera Interface 0 votes 87 views 0 replies Started yesterday by Kiran bhat Answer this
Suggested answer Store operations where the cache line is already cached (ACE protocol)
  • AMBA
  • AMBA 4
  • AXI
  • Interface
2 votes 6213 views 9 replies Latest yesterday by het Answer this
Not answered Best most recent text on ARM arch 0 votes 185 views 0 replies Started 4 days ago by d.ry Answer this
Not answered Readunique and cleanunique transactions in ACE protocol
  • AMBA
  • AMBA 4
  • AXI4
0 votes 167 views 0 replies Started 4 days ago by het Answer this
Suggested answer Raspberry pi 3 and .net 5 coreclr 1 votes 2079 views 2 replies Latest 5 days ago by delinaty Answer this
Not answered CHI protocol cache line states Started 23 hours ago by S_Seth 0 replies 136 views
Not answered STM32F769i-Discovery IP Camera Interface Started yesterday by Kiran bhat 0 replies 87 views
Suggested answer Store operations where the cache line is already cached (ACE protocol) Latest yesterday by het 9 replies 6213 views
Not answered Best most recent text on ARM arch Started 4 days ago by d.ry 0 replies 185 views
Not answered Readunique and cleanunique transactions in ACE protocol Started 4 days ago by het 0 replies 167 views
Suggested answer Raspberry pi 3 and .net 5 coreclr Latest 5 days ago by delinaty 2 replies 2079 views