System Trace Macrocell

Getting Started

The Arm CoreSight System Trace Macrocell (STM) is a trace source that enables real-time instrumentation of software with no impact on system behavior or performance. For software, system and hardware engineers, visibility of the complete system is now critical. This is due to the need to deliver high performance, power optimized systems in shorter development cycles.

The Arm CoreSight System Trace Macrocell (STM) extends low-cost real-time visibility of software and hardware execution to all software developers. In particular application and kernel developers, enabling rich, optimized and low power software on Arm processor-powered devices across the whole supply chain.

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

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CoreSight technical introduction

Learn about the basics of Arm CoreSight debug and trace technology, and how to implement it in a system.
Read here
Introduction to CoreSight SoC-400

This short video introduces the motivation behind the requirement for debug and trace, and provides an overview of how CoreSight SoC-400 can help build this functionality into SoC designs.
Watch video
Better trace for better software with Arm CoreSight

This white paper explores the limitations of existing software debug and trace technologies, and explains how the Arm CoreSight System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, at the same time as applying existing open source trace infrastructures.
Read here
Low pin-count debug interfaces for multi-device systems

This white paper examines some alternatives to JTAG as a debug interface, and concludes that a serial wire debug interface can be delivered with lower pin-count and higher performance, and maintain support for multiprocessor systems and interoperability with test.
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Key steps to create a debug and trace solution for an Arm SoC

The global cost of debugging software has risen to $312 billion annually. This whitepaper outlines the key steps to create a debug and trace solution for an Arm SoC.
Read here

Community Blogs

Arm and ETAS partner to optimize model-based development for Arm devices

Arm and ETAS bring optimum runtime performance and simplified development flow for model-based development and automated code generation in safety applications

3 months ago by Guilherme Marshall

The Flexible Approach to Adding Functional Safety to a CPU

Find out more about Functional Safety with SoC designs and Software Test Libraries.

5 months ago by Naresh Menon

The Future of Safety in the Digital Cockpit

Developed with support from Arm, CoreAVI brings to market a comprehensive suite of graphics and compute drivers and libraries that will be certifiable for use in ISO 26262 ASIL D applications, for Arm’s latest Mali-G78AE GPU IP.

6 months ago by Daniel Bernal

Take the fast track to autonomy with software tools for Cortex-A78AE and Ma

In this blog, read about how to fast track development to autonomy with software tools for the latest Cortex-A78AE and Mali-G78AE IP.

6 months ago by Ronan Synnott

Mali-G78AE: Arm’s First High-Performance GPU with Functional Safety

Arm has brought to market its first high performance GPU with functional safety, Mali-G78AE.

6 months ago by Jake Kochnowicz

Arm Mali-C71AE: High performance Image Signal Processing with Advanced Safe

Mali-C71AE will be Arm’s highest performance image signal processor (ISP) now with comprehensive safety capability.

6 months ago by Graeme Voller

Community Forums

Answered	Forum FAQs ARM Community	3361 views	0 replies	Started 4 months ago by Annie	Answer this
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Suggested answer	Cortex M4 hard fault finding root cause on LPC4078 pc=0x0 R15 (PC Program Counter) 3 (HardFault)	1771 views	15 replies	Latest 3 days ago by tobermory	Answer this
Suggested answer	ARM Cortex ICode, DCode, System buses APB AMBA SRAM Cortex-M3 Bus Architecture Cortex-M Memory	15500 views	9 replies	Latest 8 days ago by ele	Answer this

Answered	Forum FAQs Started 4 months ago by Annie	0 replies 3361 views
Answered	Forum FAQs Started 4 months ago by Annie	0 replies 3269 views
Not answered	2-D Convolution with CMSIS Started 9 hours ago by icebeing	0 replies 29 views
Not answered	How to determine HREADY during master change the selected slave? Started 12 hours ago by jack5566	0 replies 25 views
Suggested answer	Cortex M4 hard fault finding root cause on LPC4078 pc=0x0 Latest 3 days ago by tobermory	15 replies 1771 views
Suggested answer	ARM Cortex ICode, DCode, System buses Latest 8 days ago by ele	9 replies 15500 views