System Trace Macrocell

Getting Started

The Arm CoreSight System Trace Macrocell (STM) is a trace source that enables real-time instrumentation of software with no impact on system behavior or performance. For software, system and hardware engineers, visibility of the complete system is now critical. This is due to the need to deliver high performance, power optimized systems in shorter development cycles.

The Arm CoreSight System Trace Macrocell (STM) extends low-cost real-time visibility of software and hardware execution to all software developers. In particular application and kernel developers, enabling rich, optimized and low power software on Arm processor-powered devices across the whole supply chain.

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

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CoreSight technical introduction

Learn about the basics of Arm CoreSight debug and trace technology, and how to implement it in a system.
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Introduction to CoreSight SoC-400

This short video introduces the motivation behind the requirement for debug and trace, and provides an overview of how CoreSight SoC-400 can help build this functionality into SoC designs.
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Better trace for better software with Arm CoreSight

This white paper explores the limitations of existing software debug and trace technologies, and explains how the Arm CoreSight System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, at the same time as applying existing open source trace infrastructures.
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Low pin-count debug interfaces for multi-device systems

This white paper examines some alternatives to JTAG as a debug interface, and concludes that a serial wire debug interface can be delivered with lower pin-count and higher performance, and maintain support for multiprocessor systems and interoperability with test.
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Key steps to create a debug and trace solution for an Arm SoC

The global cost of debugging software has risen to $312 billion annually. This whitepaper outlines the key steps to create a debug and trace solution for an Arm SoC.
Read here

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1 months ago by Antonio Priore

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Community Forums

Not answered	AXI fixed burst to a slave with narrow data width AXI AXI4 Bus Architecture	10 views	0 replies	Started yesterday by Sana	Answer this
Suggested answer	NOR, SPI, U-Boot, Kernal	70 views	2 replies	Latest yesterday by Andy Neil	Answer this
Answered	Regarding implementation of a scenario in AHB protocol	118 views	4 replies	Latest 2 days ago by Suyash Sharma	Answer this
Suggested answer	How could CMN600 route snoop transactions to RN-F	316 views	2 replies	Latest 3 days ago by Joe Chen	Answer this
Suggested answer	Application scenarios of APB4	329 views	1 replies	Latest 4 days ago by Christopher Tory	Answer this
Suggested answer	Outstanding support in AXI slave	274 views	1 replies	Latest 4 days ago by Christopher Tory	Answer this

Not answered	AXI fixed burst to a slave with narrow data width Started yesterday by Sana	0 replies 10 views
Suggested answer	NOR, SPI, U-Boot, Kernal Latest yesterday by Andy Neil	2 replies 70 views
Answered	Regarding implementation of a scenario in AHB protocol Latest 2 days ago by Suyash Sharma	4 replies 118 views
Suggested answer	How could CMN600 route snoop transactions to RN-F Latest 3 days ago by Joe Chen	2 replies 316 views
Suggested answer	Application scenarios of APB4 Latest 4 days ago by Christopher Tory	1 replies 329 views
Suggested answer	Outstanding support in AXI slave Latest 4 days ago by Christopher Tory	1 replies 274 views