System Trace Macrocell

Getting Started

The Arm CoreSight System Trace Macrocell (STM) is a trace source that enables real-time instrumentation of software with no impact on system behavior or performance. For software, system and hardware engineers, visibility of the complete system is now critical. This is due to the need to deliver high performance, power optimized systems in shorter development cycles.

The Arm CoreSight System Trace Macrocell (STM) extends low-cost real-time visibility of software and hardware execution to all software developers. In particular application and kernel developers, enabling rich, optimized and low power software on Arm processor-powered devices across the whole supply chain.

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

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CoreSight technical introduction

Learn about the basics of Arm CoreSight debug and trace technology, and how to implement it in a system.
Read here
Introduction to CoreSight SoC-400

This short video introduces the motivation behind the requirement for debug and trace, and provides an overview of how CoreSight SoC-400 can help build this functionality into SoC designs.
Watch video
Better trace for better software with Arm CoreSight

This white paper explores the limitations of existing software debug and trace technologies, and explains how the Arm CoreSight System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, at the same time as applying existing open source trace infrastructures.
Read here
Low pin-count debug interfaces for multi-device systems

This white paper examines some alternatives to JTAG as a debug interface, and concludes that a serial wire debug interface can be delivered with lower pin-count and higher performance, and maintain support for multiprocessor systems and interoperability with test.
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Key steps to create a debug and trace solution for an Arm SoC

The global cost of debugging software has risen to $312 billion annually. This whitepaper outlines the key steps to create a debug and trace solution for an Arm SoC.
Read here

Community Blogs

AMBA ATP Engine 3.1: programmable traffic generation

In this blog, read about the AMBA ATP 3.1 release for programmable traffic generation.

1 months ago by Adrian Herrera

Arm and ETAS partner to optimize model-based development for Arm devices

Arm and ETAS bring optimum runtime performance and simplified development flow for model-based development and automated code generation in safety applications

6 months ago by Guilherme Marshall

The Flexible Approach to Adding Functional Safety to a CPU

Find out more about Functional Safety with SoC designs and Software Test Libraries.

9 months ago by Naresh Menon

The Future of Safety in the Digital Cockpit

Developed with support from Arm, CoreAVI brings to market a comprehensive suite of graphics and compute drivers and libraries that will be certifiable for use in ISO 26262 ASIL D applications, for Arm’s latest Mali-G78AE GPU IP.

10 months ago by Daniel Bernal

Take the fast track to autonomy with software tools for Cortex-A78AE and Ma

In this blog, read about how to fast track development to autonomy with software tools for the latest Cortex-A78AE and Mali-G78AE IP.

10 months ago by Ronan Synnott

Mali-G78AE: Arm’s First High-Performance GPU with Functional Safety

Arm has brought to market its first high performance GPU with functional safety, Mali-G78AE.

10 months ago by Jake Kochnowicz

Community Forums

Answered	Forum FAQs ARM Community	5556 views	0 replies	Started 8 months ago by Annie	Answer this
Answered	Forum FAQs ARM Community	4566 views	0 replies	Started 8 months ago by Annie	Answer this
Not answered	Unaligned transfer pattern in AXI4 Protocols	121 views	0 replies	Started yesterday by Supal	Answer this
Not answered	AHB - continue the transfer after an error response	272 views	0 replies	Started yesterday by Joon Hong	Answer this
Not answered	Flash Patching in Cortex M7 Arm7 Cortex-M7 System architectures	364 views	0 replies	Started 2 days ago by SaiGautamJP	Answer this
Answered	HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2)	553 views	2 replies	Latest 3 days ago by Tapas	Answer this

Answered	Forum FAQs Started 8 months ago by Annie	0 replies 5556 views
Answered	Forum FAQs Started 8 months ago by Annie	0 replies 4566 views
Not answered	Unaligned transfer pattern in AXI4 Started yesterday by Supal	0 replies 121 views
Not answered	AHB - continue the transfer after an error response Started yesterday by Joon Hong	0 replies 272 views
Not answered	Flash Patching in Cortex M7 Started 2 days ago by SaiGautamJP	0 replies 364 views
Answered	HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2) Latest 3 days ago by Tapas	2 replies 553 views