System Trace Macrocell

Getting Started

The Arm CoreSight System Trace Macrocell (STM) is a trace source that enables real-time instrumentation of software with no impact on system behavior or performance. For software, system and hardware engineers, visibility of the complete system is now critical. This is due to the need to deliver high performance, power optimized systems in shorter development cycles.

The Arm CoreSight System Trace Macrocell (STM) extends low-cost real-time visibility of software and hardware execution to all software developers. In particular application and kernel developers, enabling rich, optimized and low power software on Arm processor-powered devices across the whole supply chain.

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

Learn more

CoreSight technical introduction

Learn about the basics of Arm CoreSight debug and trace technology, and how to implement it in a system.
Read here
Introduction to CoreSight SoC-400

This short video introduces the motivation behind the requirement for debug and trace, and provides an overview of how CoreSight SoC-400 can help build this functionality into SoC designs.
Watch video
Better trace for better software with Arm CoreSight

This white paper explores the limitations of existing software debug and trace technologies, and explains how the Arm CoreSight System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, at the same time as applying existing open source trace infrastructures.
Read here
Low pin-count debug interfaces for multi-device systems

This white paper examines some alternatives to JTAG as a debug interface, and concludes that a serial wire debug interface can be delivered with lower pin-count and higher performance, and maintain support for multiprocessor systems and interoperability with test.
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Key steps to create a debug and trace solution for an Arm SoC

The global cost of debugging software has risen to $312 billion annually. This whitepaper outlines the key steps to create a debug and trace solution for an Arm SoC.
Read here

Community Blogs

Simplifying workload modeling with AMBA ATP Engine

Following the release of the AMBA Adaptive Traffic Profiles (ATP) Specification, we are pleased to announce the AMBA ATP Engine, to further facilitate ATP’s adoption into a variety of platforms.

11 days ago by Francisco Socal

Development of Arm based systems with Synopsys Virtual Prototyping:…

Find out more about virtual prototyping from Synopsys as thousands of engineers around the world have been asked to work from home.

26 days ago by Jason Andrews

Accelerating Innovation for Safety Systems with Arm Flexible Access

Arm is proud to announce the addition of Arm Safety Packages for select IP within Arm Flexible Access, with the goal to make it easier for developers in the automotive and other safety-related industries to create SoCs.

3 months ago by Chet Babla

Functional Safety on Arm – Beyond Automotive

Arm has moved a long way from the days where our only ‘safety’ requirement was to provide ECC or parity protections on CPU RAMs and we are now able to offer a number of System IP, GPUs, ISPs and NPUs as Safety Ready products. With Arm’s extensive…

5 months ago by Antonio Priore

Docker enables Arm Cycle Model Studio on Ubuntu

Arm Cycle Model Studio (CMS) is a great tool to create SystemC simulation models from Verilog RTL source code. This articles shows how to use Docker to run CMS and create models on an Ubuntu machine.

7 months ago by Jason Andrews

Leading the Digital Transformation of the Car at IAA Frankfurt

This week at IAA New Mobility World, to demonstrate the future of in-car experiences, we are exhibiting a market-ready, scalable infotainment and cockpit control system from MediaTek and Mobica, featuring TomTom Navigation.

8 months ago by Andy Moore

Community Forums

Suggested answer	AMBA AXI reset AMBA AXI	6794 views	2 replies	Latest yesterday by Ravi V.	Answer this
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Answered	strobe	5513 views	3 replies	Latest 3 days ago by Christopher Tory	Answer this
Not answered	BUSY transfer just before the last transfer in a burst by a AHB Master.	355 views	0 replies	Started 3 days ago by ISHWAR GANIGER	Answer this
Suggested answer	PADDR APB vhdl AMBA 3 APB Interface	685 views	1 replies	Latest 5 days ago by Colin Campbell	Answer this
Not answered	ABP wrapper/ resizer 32-128 bit FPGA SoC APB vhdl 128-bit SoC FPGA	612 views	0 replies	Started 9 days ago by Rann	Answer this

Suggested answer	AMBA AXI reset Latest yesterday by Ravi V.	2 replies 6794 views
Suggested answer	optimize scaling that involves float division in M0 Latest yesterday by Broeker	2 replies 3090 views
Answered	strobe Latest 3 days ago by Christopher Tory	3 replies 5513 views
Not answered	BUSY transfer just before the last transfer in a burst by a AHB Master. Started 3 days ago by ISHWAR GANIGER	0 replies 355 views
Suggested answer	PADDR Latest 5 days ago by Colin Campbell	1 replies 685 views
Not answered	ABP wrapper/ resizer 32-128 bit FPGA SoC Started 9 days ago by Rann	0 replies 612 views