CoreSight Trace Memory Controller (TMC)

Key features

A TMC has three configuration options:

• Embedded Trace Buffer: Offers a circular buffer to store trace. It shares the programmers model with the SoC-400-delivered ETB, but adds support for up to 4GB of SRAM. No trace can be read until trace capture has stopped. In this mode, trace capture can automatically stop after receiving a trigger signal. If data is read out fast enough, then the oldest samples are over-written.

• Embedded Trace FIFO (ETF): Stores trace into dedicated SRAM, with the buffer behavior programmed using an APB interface to either behave as a FIFO or as a circular buffer. It can be used to average peak trace bandwidth and reduce bandwidth requirements on the trace port. No trace is lost or overwritten. Instead, back pressure is applied to the source when the FIFO is full.

• Embedded Trace Router (ETR): Terminates a trace bus and converts the format to AXI, routed to either system memory or any other AXI slave.

In all TMC configurations, an APB interface is also present, to enable runtime control of the TMC behavior.

Embedded Trace FIFO

Enables trace to be stored in a dedicated SRAM, used either as a circular buffer or as a FIFO. The functionality of this configuration is a superset of the functionality of the ETB configuration.

Embedded Trace Buffer (ETB)

Enables trace to be stored in a dedicated SRAM, used as a circular buffer. This configuration is similar to the CoreSight ETB.