CoreSight Trace Memory Controller (TMC)

Key features

A TMC has three configuration options:

• Embedded Trace Buffer: Offers a circular buffer to store trace. It shares the programmers model with the SoC-400-delivered ETB, but adds support for up to 4GB of SRAM. No trace can be read until trace capture has stopped. In this mode, trace capture can automatically stop after receiving a trigger signal. If data is read out fast enough, then the oldest samples are over-written.

• Embedded Trace FIFO (ETF): Stores trace into dedicated SRAM, with the buffer behavior programmed using an APB interface to either behave as a FIFO or as a circular buffer. It can be used to average peak trace bandwidth and reduce bandwidth requirements on the trace port. No trace is lost or overwritten. Instead, back pressure is applied to the source when the FIFO is full.

• Embedded Trace Router (ETR): Terminates a trace bus and converts the format to AXI, routed to either system memory or any other AXI slave.

In all TMC configurations, an APB interface is also present, to enable runtime control of the TMC behavior.

Use cases

The TMC supports real-time trace export or capture on-chip as follow:

Customer Successes

"Arm CoreSight debug and trace technology was instrumental to the successful bring-up of the Exynos 7870. When designers are working on optimizations to eke out the maximum performance, there is peace of mind in knowing that CoreSight gives the best real-time trace delivering visibility onto the chip fast in order to fine tune the performance" Samsung Exynos 7870

"In addition, Arm CoreSight debug and trace technology was implemented in the chip’s development to provide on-chip visibility that enables fast diagnosis of bugs and performance analysis. Amongst other things, CoreSight ensures it meets the high quality standards required by ISO 26262." Xilinx Zynq-7000