The Arm CoreSight Trace Memory Controller (TMC)

CoreSight Trace Memory Controller Chip.

Getting Started

The Arm CoreSight Trace Memory Controller (TMC) is a configurable trace component to terminate trace buses into buffers, FIFOs, or alternatively, to route trace data over AXI to memory or off-chip to interface controllers.

Key features

A TMC has three configuration options:

  • Embedded Trace Buffer: Offers a circular buffer to store trace. It shares the programmers model with the SoC-400-delivered ETB, but adds support for up to 4GB of SRAM. No trace can be read until trace capture has stopped. In this mode, trace capture can automatically stop after receiving a trigger signal. If data is read out fast enough, then the oldest samples are over-written.
  • Embedded Trace FIFO (ETF): Stores trace into dedicated SRAM, with the buffer behavior programmed using an APB interface to either behave as a FIFO or as a circular buffer. It can be used to average peak trace bandwidth and reduce bandwidth requirements on the trace port. No trace is lost or overwritten. Instead, back pressure is applied to the source when the FIFO is full.
  • Embedded Trace Router (ETR): Terminates a trace bus and converts the format to AXI, routed to either system memory or any other AXI slave.

In all TMC configurations, an APB interface is also present, to enable runtime control of the TMC behavior.

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Embedded Trace FIFO

Enables trace to be stored in a dedicated SRAM, used either as a circular buffer or as a FIFO. The functionality of this configuration is a superset of the functionality of the ETB configuration.

Embedded Trace Buffer (ETB)

Enables trace to be stored in a dedicated SRAM, used as a circular buffer. This configuration is similar to the CoreSight ETB.

Use cases

The TMC supports real-time trace export or capture on-chip as follow:

Mode

Usage case

Benefits

Real-time streaming through the trace port(TPIU)

Export real-time trace through a dedicated trace port.

Provide off-chip and high bandwidth real-time trace for all the SoC trace macrocells.

Real-time streaming through the debug interface (JTAG or 2-pin Serial Wire Debug)

Export real-time low bandwidth system trace.

Enable system level debug & optimization of production silicon in final product for system tuning, failure analysis and maintenance.

Real-time streaming through SoC I/O controllers

Export real-time trace through dedicated or shared I/O controllers.

When implemented with High Speed Serial Trace Port, enables real-time trace export using Gbit serial ports. When implemented with functional I/O controllers, enables re-use of SoC resources removing the need of dedicated trace ports.

Trace capture on-chip using system memory (several MBytes)

MBytes of system memory can be allocated by the s/w & OS for real-time trace.

Remove need for dedicated trace port and enable s/w developers to use as required system memory to debug and optimize their product.

Trace capture using dedicated SRAM (ETB with few KBytes of SRAM)

Dedicated SRAM to capture trace.

Provide trace when trace port not available; no intrusion with system memory.

  • Manual containing technical information.

  • CoreSight TMC Technical Reference Manual

    For system designers, system integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Read here
  • A program that is running on a desktop.

  • CoreSight technical introduction

    Learn about the basics of Arm CoreSight debug and trace technology, and how to implement it in a system.

    Read here
  • A program that is running on a desktop.

  • Introduction to CoreSight SoC-400

    This short video introduces the motivation behind the requirement for debug and trace, and provides an overview of how CoreSight SoC-400 can help build this functionality into SoC designs.

    Watch video
  • A program that is running on a desktop.

  • Better trace for better software with Arm CoreSight

    This white paper explores the limitations of existing software debug and trace technologies, and explains how the Arm CoreSight System Trace Macrocell (STM) and Trace Memory Controller (TMC) enable system level visibility to more developers. This reduces latency and increases throughput, at the same time as applying existing open source trace infrastructures.

    Read here
  • A program that is running on a desktop.

  • Low pin-count debug interfaces for multi-device systems

    This white paper examines some alternatives to JTAG as a debug interface, and concludes that a serial wire debug interface can be delivered with lower pin-count and higher performance, and maintain support for multiprocessor systems and interoperability with test.

    Read here
  • A development Board.

  • Key steps to create a debug and trace solution for an Arm SoC

    The global cost of debugging software has risen to $312 billion annually. This white paper outlines the key steps to create a debug and trace solution for an Arm SoC.

    Read here

Customer Successes

Samsung

"Arm CoreSight debug and trace technology was instrumental to the successful bring-up of the Exynos 7870. When designers are working on optimizations to eke out the maximum performance, there is peace of mind in knowing that CoreSight gives the best real-time trace delivering visibility onto the chip fast in order to fine tune the performance" Samsung Exynos 7870

Xilinx

"In addition, Arm CoreSight debug and trace technology was implemented in the chip’s development to provide on-chip visibility that enables fast diagnosis of bugs and performance analysis. Amongst other things, CoreSight ensures it meets the high quality standards required by ISO 26262." Xilinx Zynq-7000

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Community Forums

Not answered AXI fixed burst to a slave with narrow data width
  • AXI
  • AXI4
  • Bus Architecture
 0 votes 2 views 0 replies Started 6 hours ago by Sana Answer this
Suggested answer NOR, SPI, U-Boot, Kernal 0 votes 53 views 2 replies Latest 23 hours ago by Andy Neil Answer this
Answered Regarding implementation of a scenario in AHB protocol 0 votes 85 views 4 replies Latest yesterday by Suyash Sharma Answer this
Suggested answer How could CMN600 route snoop transactions to RN-F 0 votes 290 views 2 replies Latest 2 days ago by Joe Chen Answer this
Suggested answer Application scenarios of APB4 0 votes 318 views 1 replies Latest 3 days ago by Christopher Tory Answer this
Suggested answer Outstanding support in AXI slave 0 votes 262 views 1 replies Latest 3 days ago by Christopher Tory Answer this
Not answered AXI fixed burst to a slave with narrow data width Started 6 hours ago by Sana 0 replies 2 views
Suggested answer NOR, SPI, U-Boot, Kernal Latest 23 hours ago by Andy Neil 2 replies 53 views
Answered Regarding implementation of a scenario in AHB protocol Latest yesterday by Suyash Sharma 4 replies 85 views
Suggested answer How could CMN600 route snoop transactions to RN-F Latest 2 days ago by Joe Chen 2 replies 290 views
Suggested answer Application scenarios of APB4 Latest 3 days ago by Christopher Tory 1 replies 318 views
Suggested answer Outstanding support in AXI slave Latest 3 days ago by Christopher Tory 1 replies 262 views