Getting Started

Optimized and efficient access to the DRAM is critical to the performance of any chip. As the number of processing elements on a chip increases, so does the demand for data. With DRAM technology transitioning to DDR4 for infrastructure and LPDDR4 for mobile and consumer applications, not only does the frequency of DRAM operation increase significantly, but also the complexity of making the best use of the DRAM bandwidth to deliver high Quality of Service (QoS) at low power, increases. Managing the differing demands of multiple processing elements while delivering maximum DRAM bandwidth is the primary challenge addressed by the Dynamic Memory Controller (DMC).

The Dynamic Memory Controller family

CoreLink DMC-500 Dynamic Memory Controller

CoreLink DMC-500 Dynamic Memory Controller

  • Specifically designed for low power operation in mobile, consumer and embedded applications that utilize LPDDR4 and LPDDR3 memories
  • Optimized for best memory bandwidth at low latencies with Arm CoreLink CCI and NIC




CoreLink DMC-520 Dynamic Memory Controller

CoreLink DMC-520 Dynamic Memory Controller

  • Targeted at applications in server, networking and high-performance computing, using DDR4 and DDR3 memories
  • Supports enterprise-class requirements for high-density DIMMs, error correction codes and reliability with ease-of-use Optimized for highest performance with the CoreLink CCN family


DMC-620

CoreLink DMC-620 Dynamic Memory Controller

  • Builds on top of DMC-520 features to provide the best performance with RAS and end-to-end QoS support with CoreLink CMN-600.
  • Reduces static pipeline latency by up to 50% compared to DMC-520. Expands support for 3DS DRAM with extended virtual rank support.
  • Improves memory access latency for Arm Cortex v8-A processors significantly under common operating conditions.


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Suggested answer How feasible and what is the API for packet filtering at harware level (using Trust zone)? Latest 21 hours ago by Oliver Beirne 1 replies 515 views
Not answered What purpose does SINGLE BURST feature in AHB serve? Started yesterday by SophiaTrang 0 replies 127 views
Suggested answer Trustzone impact on battery ? Latest yesterday by Andy Neil 1 replies 140 views
Not answered what is different that change start address and use WSTRB signal for transfer Started yesterday by ajskdlf 0 replies 136 views
Suggested answer Any possibilities to automate the image flash into the target other than UMS Latest 2 days ago by Srinuvasan 2 replies 186 views
Suggested answer What is peripheral and why use low-power in AXI Latest 2 days ago by Colin Campbell 1 replies 176 views