Getting Started

Optimized and efficient access to the DRAM is critical to the performance of any chip. As the number of processing elements on a chip increases, so does the demand for data. With DRAM technology transitioning to DDR4 for infrastructure and LPDDR4 for mobile and consumer applications, not only does the frequency of DRAM operation increase significantly, but also the complexity of making the best use of the DRAM bandwidth to deliver high Quality of Service (QoS) at low power, increases. Managing the differing demands of multiple processing elements while delivering maximum DRAM bandwidth is the primary challenge addressed by the Dynamic Memory Controller (DMC).

The Dynamic Memory Controller family

CoreLink DMC-500 Dynamic Memory Controller

CoreLink DMC-500 Dynamic Memory Controller

  • Specifically designed for low power operation in mobile, consumer and embedded applications that utilize LPDDR4 and LPDDR3 memories
  • Optimized for best memory bandwidth at low latencies with Arm CoreLink CCI and NIC




CoreLink DMC-520 Dynamic Memory Controller

CoreLink DMC-520 Dynamic Memory Controller

  • Targeted at applications in server, networking and high-performance computing, using DDR4 and DDR3 memories
    • Supports enterprise-class requirements for high-density DIMMs, error correction codes and reliability with ease-of-use Optimized for highest performance with the CoreLink CCN family


DMC-620

CoreLink DMC-620 Dynamic Memory Controller

  • Builds on top of DMC-520 features to provide the best performance with RAS and end-to-end QoS support with CoreLink CMN-600.
  • Reduces static pipeline latency by up to 50% compared to DMC-520. Expands support for 3DS DRAM with extended virtual rank support.
  • Improves memory access latency for Arm Cortex v8-A processors significantly under common operating conditions.

Get support

Community Blogs

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Sparking potential for community development: Arm Education Kits now…

University Program materials are now even easier to access via GitHub. Use our resources, tools and more to spark the potential of your students.

yesterday by Dipesh Patel
1
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Creating the Morello Technology Demonstrator

The goal for Arm’s Morello program has been to develop an experimental hardware technology demonstrator, in around two and half years.

5 days ago by Mark Inskip
1
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Software enablement and the Morello Technology Demonstrator

Arm's software contributions to Morello target various of open-source projects. This series of integrated software stacks target the Morello board and Morello Platform Model (FVP).

5 days ago by Mark Nicholson
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Vela Complier: The first step to deploy your NN model on the Arm Ethos-U mi

As first step to deploy your NN model on Ethos-U, Vela Complier is open-source and easy-use. Try it out and embrace the improvement of ML ability brought by Ethos-U to embedded system.

7 days ago by Liliya Wu
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Works on Arm welcomes a new Community Hardware Program

miniNodes is proud to host and manage the brand new Arm Community Developer Hardware Program with the goal of providing individual developers access to single board computers from an array of vendors.

10 days ago by fixxxer
2
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Optimize a ML model for fast inference on Ethos-U microNPU

This blog post explains how to optimize a trained deep neural network model to run on Ethos-U55 and Ethos-U65.

13 days ago by Elham Harirpoush

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