Getting Started

Optimized and efficient access to the DRAM is critical to the performance of any chip. As the number of processing elements on a chip increases, so does the demand for data. With DRAM technology transitioning to DDR4 for infrastructure and LPDDR4 for mobile and consumer applications, not only does the frequency of DRAM operation increase significantly, but also the complexity of making the best use of the DRAM bandwidth to deliver high Quality of Service (QoS) at low power, increases. Managing the differing demands of multiple processing elements while delivering maximum DRAM bandwidth is the primary challenge addressed by the Dynamic Memory Controller (DMC).

The Dynamic Memory Controller family

CoreLink DMC-500 Dynamic Memory Controller

CoreLink DMC-500 Dynamic Memory Controller

  • Specifically designed for low power operation in mobile, consumer and embedded applications that utilize LPDDR4 and LPDDR3 memories
  • Optimized for best memory bandwidth at low latencies with Arm CoreLink CCI and NIC




CoreLink DMC-520 Dynamic Memory Controller

CoreLink DMC-520 Dynamic Memory Controller

  • Targeted at applications in server, networking and high-performance computing, using DDR4 and DDR3 memories
    • Supports enterprise-class requirements for high-density DIMMs, error correction codes and reliability with ease-of-use Optimized for highest performance with the CoreLink CCN family


DMC-620

CoreLink DMC-620 Dynamic Memory Controller

  • Builds on top of DMC-520 features to provide the best performance with RAS and end-to-end QoS support with CoreLink CMN-600.
  • Reduces static pipeline latency by up to 50% compared to DMC-520. Expands support for 3DS DRAM with extended virtual rank support.
  • Improves memory access latency for Arm Cortex v8-A processors significantly under common operating conditions.

Get support

Community Blogs

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Simplifying workload modeling with AMBA ATP Engine

Following the release of the AMBA Adaptive Traffic Profiles (ATP) Specification, we are pleased to announce the AMBA ATP Engine, to further facilitate ATP’s adoption into a variety of platforms.

14 days ago by Francisco Socal
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Development of Arm based systems with Synopsys Virtual Prototyping:…

Find out more about virtual prototyping from Synopsys as thousands of engineers around the world have been asked to work from home.

29 days ago by Jason Andrews
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Accelerating Innovation for Safety Systems with Arm Flexible Access

Arm is proud to announce the addition of Arm Safety Packages for select IP within Arm Flexible Access, with the goal to make it easier for developers in the automotive and other safety-related industries to create SoCs.

3 months ago by Chet Babla
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Functional Safety on Arm – Beyond Automotive

Arm has moved a long way from the days where our only ‘safety’ requirement was to provide ECC or parity protections on CPU RAMs and we are now able to offer a number of System IP, GPUs, ISPs and NPUs as Safety Ready products. With Arm’s extensive…

5 months ago by Antonio Priore
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Docker enables Arm Cycle Model Studio on Ubuntu

Arm Cycle Model Studio (CMS) is a great tool to create SystemC simulation models from Verilog RTL source code. This articles shows how to use Docker to run CMS and create models on an Ubuntu machine.

7 months ago by Jason Andrews
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Leading the Digital Transformation of the Car at IAA Frankfurt

This week at IAA New Mobility World, to demonstrate the future of in-car experiences, we are exhibiting a market-ready, scalable infotainment and cockpit control system from MediaTek and Mobica, featuring TomTom Navigation.

8 months ago by Andy Moore

Community Forums

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 0 votes 747 views 0 replies Started 12 days ago by Rann Answer this
Suggested answer BUSY transfer just before the last transfer in a burst by a AHB Master. Latest 2 days ago by Colin Campbell 1 replies 604 views
Suggested answer AMBA AXI reset Latest 2 days ago by Colin Campbell 3 replies 7065 views
Suggested answer optimize scaling that involves float division in M0 Latest 4 days ago by Broeker 2 replies 3253 views
Answered strobe Latest 6 days ago by Christopher Tory 3 replies 5741 views
Suggested answer PADDR Latest 8 days ago by Colin Campbell 1 replies 847 views
Not answered ABP wrapper/ resizer 32-128 bit FPGA SoC Started 12 days ago by Rann 0 replies 747 views