Getting Started

Optimized and efficient access to the DRAM is critical to the performance of any chip. As the number of processing elements on a chip increases, so does the demand for data. With DRAM technology transitioning to DDR4 for infrastructure and LPDDR4 for mobile and consumer applications, not only does the frequency of DRAM operation increase significantly, but also the complexity of making the best use of the DRAM bandwidth to deliver high Quality of Service (QoS) at low power, increases. Managing the differing demands of multiple processing elements while delivering maximum DRAM bandwidth is the primary challenge addressed by the Dynamic Memory Controller (DMC).

The Dynamic Memory Controller family

CoreLink DMC-500 Dynamic Memory Controller

CoreLink DMC-500 Dynamic Memory Controller

  • Specifically designed for low power operation in mobile, consumer and embedded applications that utilize LPDDR4 and LPDDR3 memories
  • Optimized for best memory bandwidth at low latencies with Arm CoreLink CCI and NIC




CoreLink DMC-520 Dynamic Memory Controller

CoreLink DMC-520 Dynamic Memory Controller

  • Targeted at applications in server, networking and high-performance computing, using DDR4 and DDR3 memories
  • Supports enterprise-class requirements for high-density DIMMs, error correction codes and reliability with ease-of-use Optimized for highest performance with the CoreLink CCN family


DMC-620

CoreLink DMC-620 Dynamic Memory Controller

  • Builds on top of DMC-520 features to provide the best performance with RAS and end-to-end QoS support with CoreLink CMN-600.
  • Reduces static pipeline latency by up to 50% compared to DMC-520. Expands support for 3DS DRAM with extended virtual rank support.
  • Improves memory access latency for Arm Cortex v8-A processors significantly under common operating conditions.


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Suggested answer BUSY transfer just before the last transfer in a burst by a AHB Master. 0 votes 604 views 1 replies Latest 2 days ago by Colin Campbell Answer this
Suggested answer AMBA AXI reset
  • AMBA
  • AXI
0 votes 7065 views 3 replies Latest 2 days ago by Colin Campbell Answer this
Suggested answer optimize scaling that involves float division in M0
  • Cortex-M0
  • Floating-Point Execution
0 votes 3253 views 2 replies Latest 4 days ago by Broeker Answer this
Answered strobe 0 votes 5741 views 3 replies Latest 6 days ago by Christopher Tory Answer this
Suggested answer PADDR
  • APB
  • vhdl
  • AMBA 3 APB Interface
0 votes 847 views 1 replies Latest 8 days ago by Colin Campbell Answer this
Not answered ABP wrapper/ resizer 32-128 bit FPGA SoC
  • APB
  • vhdl
  • 128-bit
  • SoC FPGA
0 votes 747 views 0 replies Started 12 days ago by Rann Answer this
Suggested answer BUSY transfer just before the last transfer in a burst by a AHB Master. Latest 2 days ago by Colin Campbell 1 replies 604 views
Suggested answer AMBA AXI reset Latest 2 days ago by Colin Campbell 3 replies 7065 views
Suggested answer optimize scaling that involves float division in M0 Latest 4 days ago by Broeker 2 replies 3253 views
Answered strobe Latest 6 days ago by Christopher Tory 3 replies 5741 views
Suggested answer PADDR Latest 8 days ago by Colin Campbell 1 replies 847 views
Not answered ABP wrapper/ resizer 32-128 bit FPGA SoC Started 12 days ago by Rann 0 replies 747 views