Getting Started

Optimized and efficient access to the DRAM is critical to the performance of any chip. As the number of processing elements on a chip increases, so does the demand for data. With DRAM technology transitioning to DDR4 for infrastructure and LPDDR4 for mobile and consumer applications, not only does the frequency of DRAM operation increase significantly, but also the complexity of making the best use of the DRAM bandwidth to deliver high Quality of Service (QoS) at low power, increases. Managing the differing demands of multiple processing elements while delivering maximum DRAM bandwidth is the primary challenge addressed by the Dynamic Memory Controller (DMC).

The Dynamic Memory Controller family

CoreLink DMC-500 Dynamic Memory Controller

CoreLink DMC-500 Dynamic Memory Controller

  • Specifically designed for low power operation in mobile, consumer and embedded applications that utilize LPDDR4 and LPDDR3 memories
  • Optimized for best memory bandwidth at low latencies with Arm CoreLink CCI and NIC




CoreLink DMC-520 Dynamic Memory Controller

CoreLink DMC-520 Dynamic Memory Controller

  • Targeted at applications in server, networking and high-performance computing, using DDR4 and DDR3 memories
  • Supports enterprise-class requirements for high-density DIMMs, error correction codes and reliability with ease-of-use Optimized for highest performance with the CoreLink CCN family


DMC-620

CoreLink DMC-620 Dynamic Memory Controller

  • Builds on top of DMC-520 features to provide the best performance with RAS and end-to-end QoS support with CoreLink CMN-600.
  • Reduces static pipeline latency by up to 50% compared to DMC-520. Expands support for 3DS DRAM with extended virtual rank support.
  • Improves memory access latency for Arm Cortex v8-A processors significantly under common operating conditions.


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Arm support

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Community Blogs

Community Forums

Answered how to calculate unaligned address for APB? 0 votes 260 views 6 replies Latest 5 hours ago by aditya raja Answer this
Answered why PSTRB signal in APB4 have four bits?
  • APB
  • AMBA
  • AMBA 4
0 votes 1116 views 4 replies Latest 22 hours ago by Colin Campbell Answer this
Suggested answer what is unaligned address access? 0 votes 80 views 1 replies Latest yesterday by Christopher Tory Answer this
Not answered MSP432+BLE+ Debugger interfacing 0 votes 55 views 0 replies Started 4 days ago by Devudu Answer this
Suggested answer Cache Maintenance Transactions
  • AMBA
  • ACE
  • cache
  • Interface
0 votes 986 views 8 replies Latest 5 days ago by Taniya Garg Answer this
Suggested answer AXI data channel 0 votes 159 views 1 replies Latest 6 days ago by Christopher Tory Answer this
Answered how to calculate unaligned address for APB? Latest 5 hours ago by aditya raja 6 replies 260 views
Answered why PSTRB signal in APB4 have four bits? Latest 22 hours ago by Colin Campbell 4 replies 1116 views
Suggested answer what is unaligned address access? Latest yesterday by Christopher Tory 1 replies 80 views
Not answered MSP432+BLE+ Debugger interfacing Started 4 days ago by Devudu 0 replies 55 views
Suggested answer Cache Maintenance Transactions Latest 5 days ago by Taniya Garg 8 replies 986 views
Suggested answer AXI data channel Latest 6 days ago by Christopher Tory 1 replies 159 views