Getting Started

Optimized and efficient access to the DRAM is critical to the performance of any chip. As the number of processing elements on a chip increases, so does the demand for data. With DRAM technology transitioning to DDR4 for infrastructure and LPDDR4 for mobile and consumer applications, not only does the frequency of DRAM operation increase significantly, but also the complexity of making the best use of the DRAM bandwidth to deliver high Quality of Service (QoS) at low power, increases. Managing the differing demands of multiple processing elements while delivering maximum DRAM bandwidth is the primary challenge addressed by the Dynamic Memory Controller (DMC).

The Dynamic Memory Controller family

CoreLink DMC-500 Dynamic Memory Controller

CoreLink DMC-500 Dynamic Memory Controller

  • Specifically designed for low power operation in mobile, consumer and embedded applications that utilize LPDDR4 and LPDDR3 memories
  • Optimized for best memory bandwidth at low latencies with Arm CoreLink CCI and NIC




CoreLink DMC-520 Dynamic Memory Controller

CoreLink DMC-520 Dynamic Memory Controller

  • Targeted at applications in server, networking and high-performance computing, using DDR4 and DDR3 memories
  • Supports enterprise-class requirements for high-density DIMMs, error correction codes and reliability with ease-of-use Optimized for highest performance with the CoreLink CCN family


DMC-620

CoreLink DMC-620 Dynamic Memory Controller

  • Builds on top of DMC-520 features to provide the best performance with RAS and end-to-end QoS support with CoreLink CMN-600.
  • Reduces static pipeline latency by up to 50% compared to DMC-520. Expands support for 3DS DRAM with extended virtual rank support.
  • Improves memory access latency for Arm Cortex v8-A processors significantly under common operating conditions.


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Arm support

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Not answered AXI4 ordering 0 votes 42 views 0 replies Started 19 hours ago by Hyunkyu Answer this
Answered Exception handlers and interrupt
  • CoreLink GIC-400
  • Cortex-A53
  • Corelink
  • Cortex-A5
  • Generic Interrupt Controller
  • Cortex-A
  • Interrupt
0 votes 1507 views 3 replies Latest 5 days ago by c0deface Answer this
Not answered Reading and writing to Pins in Eclipse 0 votes 670 views 0 replies Started 11 days ago by emeraldcity04 Answer this
Not answered Instruction and data cache dump from a-53 0 votes 363 views 0 replies Started 11 days ago by RCReddy Answer this
Not answered Instruction and data cache dump from a-53 0 votes 318 views 0 replies Started 11 days ago by RCReddy Answer this
Suggested answer AXI transaction failure
  • AXI4-Lite
  • AMBA 4
  • AXI
  • AXI4
0 votes 1777 views 1 replies Latest 12 days ago by Aiven16 Answer this
Not answered AXI4 ordering Started 19 hours ago by Hyunkyu 0 replies 42 views
Answered Exception handlers and interrupt Latest 5 days ago by c0deface 3 replies 1507 views
Not answered Reading and writing to Pins in Eclipse Started 11 days ago by emeraldcity04 0 replies 670 views
Not answered Instruction and data cache dump from a-53 Started 11 days ago by RCReddy 0 replies 363 views
Not answered Instruction and data cache dump from a-53 Started 11 days ago by RCReddy 0 replies 318 views
Suggested answer AXI transaction failure Latest 12 days ago by Aiven16 1 replies 1777 views