Getting Started

Optimized and efficient access to the DRAM is critical to the performance of any chip. As the number of processing elements on a chip increases, so does the demand for data. With DRAM technology transitioning to DDR4 for infrastructure and LPDDR4 for mobile and consumer applications, not only does the frequency of DRAM operation increase significantly, but also the complexity of making the best use of the DRAM bandwidth to deliver high Quality of Service (QoS) at low power, increases. Managing the differing demands of multiple processing elements while delivering maximum DRAM bandwidth is the primary challenge addressed by the Dynamic Memory Controller (DMC).

The Dynamic Memory Controller family

CoreLink DMC-500 Dynamic Memory Controller

CoreLink DMC-500 Dynamic Memory Controller

  • Specifically designed for low power operation in mobile, consumer and embedded applications that utilize LPDDR4 and LPDDR3 memories
  • Optimized for best memory bandwidth at low latencies with Arm CoreLink CCI and NIC




CoreLink DMC-520 Dynamic Memory Controller

CoreLink DMC-520 Dynamic Memory Controller

  • Targeted at applications in server, networking and high-performance computing, using DDR4 and DDR3 memories
  • Supports enterprise-class requirements for high-density DIMMs, error correction codes and reliability with ease-of-use Optimized for highest performance with the CoreLink CCN family


DMC-620

CoreLink DMC-620 Dynamic Memory Controller

  • Builds on top of DMC-520 features to provide the best performance with RAS and end-to-end QoS support with CoreLink CMN-600.
  • Reduces static pipeline latency by up to 50% compared to DMC-520. Expands support for 3DS DRAM with extended virtual rank support.
  • Improves memory access latency for Arm Cortex v8-A processors significantly under common operating conditions.


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Community Forums

Answered Forum FAQs
  • ARM Community
0 votes 7454 views 0 replies Started 10 months ago by Annie Answer this
Answered Forum FAQs
  • ARM Community
0 votes 6452 views 0 replies Started 10 months ago by Annie Answer this
Not answered uDMA Transfer
  • PrimeCell µDMAController (PL230)
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Not answered M4 Cycle count
  • Pipeline Control and Execution
  • Cortex-M4
0 votes 45 views 0 replies Started 2 days ago by PrasanthV Answer this
Suggested answer AHB - continue the transfer after an error response 0 votes 1901 views 4 replies Latest 2 days ago by Joon Hong Answer this
Suggested answer ARM Embedded Linux Course: error building image using bitbake for raspberry pi 3 0 votes 15645 views 4 replies Latest 6 days ago by Haris Suljic Answer this
Answered Forum FAQs Started 10 months ago by Annie 0 replies 7454 views
Answered Forum FAQs Started 10 months ago by Annie 0 replies 6452 views
Not answered uDMA Transfer Started 2 days ago by PrasanthV 0 replies 41 views
Not answered M4 Cycle count Started 2 days ago by PrasanthV 0 replies 45 views
Suggested answer AHB - continue the transfer after an error response Latest 2 days ago by Joon Hong 4 replies 1901 views
Suggested answer ARM Embedded Linux Course: error building image using bitbake for raspberry pi 3 Latest 6 days ago by Haris Suljic 4 replies 15645 views