Getting Started

Optimized and efficient access to the DRAM is critical to the performance of any chip. As the number of processing elements on a chip increases, so does the demand for data. With DRAM technology transitioning to DDR4 for infrastructure and LPDDR4 for mobile and consumer applications, not only does the frequency of DRAM operation increase significantly, but also the complexity of making the best use of the DRAM bandwidth to deliver high Quality of Service (QoS) at low power, increases. Managing the differing demands of multiple processing elements while delivering maximum DRAM bandwidth is the primary challenge addressed by the Dynamic Memory Controller (DMC).

The Dynamic Memory Controller family

CoreLink DMC-500 Dynamic Memory Controller

CoreLink DMC-500 Dynamic Memory Controller

  • Specifically designed for low power operation in mobile, consumer and embedded applications that utilize LPDDR4 and LPDDR3 memories
  • Optimized for best memory bandwidth at low latencies with Arm CoreLink CCI and NIC




CoreLink DMC-520 Dynamic Memory Controller

CoreLink DMC-520 Dynamic Memory Controller

  • Targeted at applications in server, networking and high-performance computing, using DDR4 and DDR3 memories
  • Supports enterprise-class requirements for high-density DIMMs, error correction codes and reliability with ease-of-use Optimized for highest performance with the CoreLink CCN family


DMC-620

CoreLink DMC-620 Dynamic Memory Controller

  • Builds on top of DMC-520 features to provide the best performance with RAS and end-to-end QoS support with CoreLink CMN-600.
  • Reduces static pipeline latency by up to 50% compared to DMC-520. Expands support for 3DS DRAM with extended virtual rank support.
  • Improves memory access latency for Arm Cortex v8-A processors significantly under common operating conditions.


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Not answered CHI protocol cache line states
  • AMBA 5 CHI
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0 votes 59 views 0 replies Started 11 hours ago by S_Seth Answer this
Not answered STM32F769i-Discovery IP Camera Interface 0 votes 81 views 0 replies Started yesterday by Kiran bhat Answer this
Suggested answer Store operations where the cache line is already cached (ACE protocol)
  • AMBA
  • AMBA 4
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2 votes 6200 views 9 replies Latest yesterday by het Answer this
Not answered Best most recent text on ARM arch 0 votes 127 views 0 replies Started 4 days ago by d.ry Answer this
Not answered Readunique and cleanunique transactions in ACE protocol
  • AMBA
  • AMBA 4
  • AXI4
0 votes 166 views 0 replies Started 4 days ago by het Answer this
Suggested answer Raspberry pi 3 and .net 5 coreclr 1 votes 2076 views 2 replies Latest 4 days ago by delinaty Answer this
Not answered CHI protocol cache line states Started 11 hours ago by S_Seth 0 replies 59 views
Not answered STM32F769i-Discovery IP Camera Interface Started yesterday by Kiran bhat 0 replies 81 views
Suggested answer Store operations where the cache line is already cached (ACE protocol) Latest yesterday by het 9 replies 6200 views
Not answered Best most recent text on ARM arch Started 4 days ago by d.ry 0 replies 127 views
Not answered Readunique and cleanunique transactions in ACE protocol Started 4 days ago by het 0 replies 166 views
Suggested answer Raspberry pi 3 and .net 5 coreclr Latest 4 days ago by delinaty 2 replies 2076 views