Getting Started

Optimized and efficient access to the DRAM is critical to the performance of any chip. As the number of processing elements on a chip increases, so does the demand for data. With DRAM technology transitioning to DDR4 for infrastructure and LPDDR4 for mobile and consumer applications, not only does the frequency of DRAM operation increase significantly, but also the complexity of making the best use of the DRAM bandwidth to deliver high Quality of Service (QoS) at low power, increases. Managing the differing demands of multiple processing elements while delivering maximum DRAM bandwidth is the primary challenge addressed by the Dynamic Memory Controller (DMC).

The Dynamic Memory Controller family

CoreLink DMC-500 Dynamic Memory Controller

CoreLink DMC-500 Dynamic Memory Controller

  • Specifically designed for low power operation in mobile, consumer and embedded applications that utilize LPDDR4 and LPDDR3 memories
  • Optimized for best memory bandwidth at low latencies with Arm CoreLink CCI and NIC




CoreLink DMC-520 Dynamic Memory Controller

CoreLink DMC-520 Dynamic Memory Controller

  • Targeted at applications in server, networking and high-performance computing, using DDR4 and DDR3 memories
  • Supports enterprise-class requirements for high-density DIMMs, error correction codes and reliability with ease-of-use Optimized for highest performance with the CoreLink CCN family


DMC-620

CoreLink DMC-620 Dynamic Memory Controller

  • Builds on top of DMC-520 features to provide the best performance with RAS and end-to-end QoS support with CoreLink CMN-600.
  • Reduces static pipeline latency by up to 50% compared to DMC-520. Expands support for 3DS DRAM with extended virtual rank support.
  • Improves memory access latency for Arm Cortex v8-A processors significantly under common operating conditions.


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Community Forums

Suggested answer How could CMN600 route snoop transactions to RN-F 0 votes 235 views 2 replies Latest 6 hours ago by Joe Chen Answer this
Suggested answer Application scenarios of APB4 0 votes 276 views 1 replies Latest 22 hours ago by Christopher Tory Answer this
Suggested answer Outstanding support in AXI slave 0 votes 213 views 1 replies Latest 22 hours ago by Christopher Tory Answer this
Answered Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior
  • AMBA
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0 votes 2832 views 5 replies Latest yesterday by Christopher Tory Answer this
Not answered Modbus port is not getting responded when there is an http request with malformed URL.
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0 votes 54 views 0 replies Started yesterday by Navaneeth Answer this
Not answered Modbus Interface
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0 votes 89 views 0 replies Started 2 days ago by Ishwariya Answer this
Suggested answer How could CMN600 route snoop transactions to RN-F Latest 6 hours ago by Joe Chen 2 replies 235 views
Suggested answer Application scenarios of APB4 Latest 22 hours ago by Christopher Tory 1 replies 276 views
Suggested answer Outstanding support in AXI slave Latest 22 hours ago by Christopher Tory 1 replies 213 views
Answered Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior Latest yesterday by Christopher Tory 5 replies 2832 views
Not answered Modbus port is not getting responded when there is an http request with malformed URL. Started yesterday by Navaneeth 0 replies 54 views
Not answered Modbus Interface Started 2 days ago by Ishwariya 0 replies 89 views