Optimized and efficient access to the DRAM is critical to the performance of any chip. As the number of processing elements on a chip increases, so does the demand for data. With DRAM technology transitioning to DDR4 for infrastructure and LPDDR4 for mobile and consumer applications, not only does the frequency of DRAM operation increase significantly, but also the complexity of making the best use of the DRAM bandwidth to deliver high Quality of Service (QoS) at low power, increases. Managing the differing demands of multiple processing elements while delivering maximum DRAM bandwidth is the primary challenge addressed by the Dynamic Memory Controller (DMC).
CoreLink DMC-520 Dynamic Memory Controller
- Targeted at applications in server, networking and high-performance computing, using DDR4 and DDR3 memories Supports enterprise-class requirements for high-density DIMMs, error correction codes and reliability with ease-of-use Optimized for highest performance with the CoreLink CCN family
CoreLink DMC-620 Dynamic Memory Controller
- Builds on top of DMC-520 features to provide the best performance with RAS and end-to-end QoS support with CoreLink CMN-600.
- Reduces static pipeline latency by up to 50% compared to DMC-520. Expands support for 3DS DRAM with extended virtual rank support.
- Improves memory access latency for Arm Cortex v8-A processors significantly under common operating conditions.
Documents and blogs that will help users design Arm-based SoCs
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|Suggested answer||Assertion for Multiple Transfer on APB Bus Latest 9 days ago by Rakesh Venkatesan||2 replies 145 views|