Getting Started

Optimized and efficient access to the DRAM is critical to the performance of any chip. As the number of processing elements on a chip increases, so does the demand for data. With DRAM technology transitioning to DDR4 for infrastructure and LPDDR4 for mobile and consumer applications, not only does the frequency of DRAM operation increase significantly, but also the complexity of making the best use of the DRAM bandwidth to deliver high Quality of Service (QoS) at low power, increases. Managing the differing demands of multiple processing elements while delivering maximum DRAM bandwidth is the primary challenge addressed by the Dynamic Memory Controller (DMC).

The Dynamic Memory Controller family

CoreLink DMC-500 Dynamic Memory Controller

CoreLink DMC-500 Dynamic Memory Controller

  • Specifically designed for low power operation in mobile, consumer and embedded applications that utilize LPDDR4 and LPDDR3 memories
  • Optimized for best memory bandwidth at low latencies with Arm CoreLink CCI and NIC




CoreLink DMC-520 Dynamic Memory Controller

CoreLink DMC-520 Dynamic Memory Controller

  • Targeted at applications in server, networking and high-performance computing, using DDR4 and DDR3 memories
  • Supports enterprise-class requirements for high-density DIMMs, error correction codes and reliability with ease-of-use Optimized for highest performance with the CoreLink CCN family


DMC-620

CoreLink DMC-620 Dynamic Memory Controller

  • Builds on top of DMC-520 features to provide the best performance with RAS and end-to-end QoS support with CoreLink CMN-600.
  • Reduces static pipeline latency by up to 50% compared to DMC-520. Expands support for 3DS DRAM with extended virtual rank support.
  • Improves memory access latency for Arm Cortex v8-A processors significantly under common operating conditions.


Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Blogs

Community Forums

Not answered SMMUv2 - Arm Corelink-MMU500 on Xilinx Zynq Ultrascale+
  • CoreLink MMU-500 System Memory Management Unit
  • Armv8-A
  • SMMUv2
0 votes 35 views 0 replies Started yesterday by Ciro Donnarumma Answer this
Suggested answer boundary concept
  • AMBA
  • AXI
  • AHB
0 votes 333 views 3 replies Latest 3 days ago by harrykayn Answer this
Suggested answer State Machine for AHB-Lite Protocol
  • ahb-lite
  • AHB
0 votes 200 views 3 replies Latest 5 days ago by Colin Campbell Answer this
Suggested answer Amba Adaptive Traffic Profiles question
  • AMBA
0 votes 130 views 1 replies Latest 8 days ago by Matteo Maria Andreozzi Answer this
Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?
  • AXI
0 votes 209 views 2 replies Latest 9 days ago by Zax Answer this
Suggested answer Assertion for Multiple Transfer on APB Bus
  • APB
  • AMBA
  • Bus Architecture
0 votes 145 views 2 replies Latest 9 days ago by Rakesh Venkatesan Answer this
Not answered SMMUv2 - Arm Corelink-MMU500 on Xilinx Zynq Ultrascale+ Started yesterday by Ciro Donnarumma 0 replies 35 views
Suggested answer boundary concept Latest 3 days ago by harrykayn 3 replies 333 views
Suggested answer State Machine for AHB-Lite Protocol Latest 5 days ago by Colin Campbell 3 replies 200 views
Suggested answer Amba Adaptive Traffic Profiles question Latest 8 days ago by Matteo Maria Andreozzi 1 replies 130 views
Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst? Latest 9 days ago by Zax 2 replies 209 views
Suggested answer Assertion for Multiple Transfer on APB Bus Latest 9 days ago by Rakesh Venkatesan 2 replies 145 views