CoreLink DMC-500

Getting Started

The CoreLink DMC-500 Dynamic Memory Controller provides power-efficient access to LPDDR4 and LPDDR3 memory in mobile, consumer, and embedded designs. The DMC-500 supports dual AXI4 system interfaces and a single DFI 4.0 memory interface.

• Delivering best performance per watt for data transfers from SoC to memory.
• Best combination of features, power, cost, and performance.
• Fast, dual-port AXI4 system interface for transferring data to LPDDR4 and LPDDR3 DRAM memories.

Specifications

Integrated TrustZone Controller

• Enabling secure media path protection for Ultra-HD content from Mali multimedia to memory.

Quality-of-Service (QoS)

• QoS improvements over previous generation reducing average and maximum CPU latency.
• End-to-end QoS optimized with CCI-550 using QoSACCEPT protocol.

CoreLink DMC-500 Characteristics

CoreLink DMC-500 utilizes LPDDR4 which is the most advanced mobile memory technology available today. LPDDR4 lowers power consumption while accessing memory due to a narrower datapath, and improves the speed at which bits are transferred to-and-from memory. System-wide QoS designed and tested with CoreLink CCI-550, CoreLink CCI-500, Cortex-A53 and Cortex-A72 processors, and Mali GPU.

Resources

Get support with Arm training courses and design reviews. You can also open a support case or manage existing cases.