The CoreLink DMC-500 Dynamic Memory Controller provides power-efficient access to LPDDR4 and LPDDR3 memory in mobile, consumer, and embedded designs. The DMC-500 supports dual AXI4 system interfaces and a single DFI 4.0 memory interface.
- Delivering best performance per watt for data transfers from SoC to memory.
- Best combination of features, power, cost, and performance.
- Fast, dual-port AXI4 system interface for transferring data to LPDDR4 and LPDDR3 DRAM memories.
|Maximum DDR speeds||LPDDR3-2133, LPDDR4-4267|
|Memory width||x32 LPDDR3, x16 LPDDR4, Dual-channel for x32 LPDDR4|
|Chip Selects (per channel)||2|
|QoS||QoS based scheduling algorithm, non-blocking paths to DRAM through CCI|
|Low power||All DRAM power modes are supported and hierarchical clock gating throughout the DMC|
CoreLink DMC-500 key features
System Optimized DMC with support for two AXI4 128-bit wide system interfaces
- One interface for channeling coherent traffic from CoreLink CCI-550 or CoreLink CCI-500 interconnect.
- One interface for supporting real-time or display, or other non-coherent traffic that demands a guaranteed maximum latency.
Single 128-bit wide DFI 4.0 memory interface
- Supporting x16 LPDDR4 up to DDR-4267 and x32 LPDDR3 up to DDR-2133 transfer, dual-DMC channel support for x32 LPDDR4.
- Support for clock gating, dynamic frequency change, and memory low-power modes for optimized power consumption.
- Integration-verified with industry-standard DFI-compatible DDR PHYs.
Integrated TrustZone Controller
- Enabling secure media path protection for Ultra-HD content from Mali multimedia to memory.
- QoS improvements over previous generation reducing average and maximum CPU latency.
- End-to-end QoS optimized with CCI-550 using QoSACCEPT protocol.
CoreLink DMC-500 Characteristics
CoreLink DMC-500 utilizes LPDDR4 which is the most advanced mobile memory technology available today. LPDDR4 lowers power consumption while accessing memory due to a narrower datapath, and improves the speed at which bits are transferred to-and-from memory. System-wide QoS designed and tested with CoreLink CCI-550, CoreLink CCI-500, Cortex-A53 and Cortex-A72 processors, and Mali GPU.
CoreLink DMC-500 Technical Reference Manual
For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.DMC-500 TRM
AMBA 4 ACE Specification
CoreLink DMC-500 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency system designs.AMBA specs
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|Answered||Forum FAQs||0 votes||2825 views||0 replies||Started 1 months ago by Annie Cracknell||Answer this|
|Answered||Forum FAQs||0 votes||2840 views||0 replies||Started 1 months ago by Annie Cracknell||Answer this|
|Not answered||Does it use a Slow Clock to turn off Main Clock?||0 votes||37 views||0 replies||Started 2 days ago by Ridge Mao||Answer this|
|Answered||Can re-order depth affect functionality of write transaction?||0 votes||529 views||5 replies||Latest 3 days ago by Colin Campbell||Answer this|
|Suggested answer||Alignment Address Calculation in AHB||0 votes||11186 views||5 replies||Latest 5 days ago by Colin Campbell||Answer this|
|Suggested answer||HTRANS when HREADY is low on the 2nd HCLK after starting the transfer||0 votes||275 views||1 replies||Latest 5 days ago by Colin Campbell||Answer this|
|Answered||Forum FAQs Started 1 months ago by Annie Cracknell||0 replies 2825 views|
|Answered||Forum FAQs Started 1 months ago by Annie Cracknell||0 replies 2840 views|
|Not answered||Does it use a Slow Clock to turn off Main Clock? Started 2 days ago by Ridge Mao||0 replies 37 views|
|Answered||Can re-order depth affect functionality of write transaction? Latest 3 days ago by Colin Campbell||5 replies 529 views|
|Suggested answer||Alignment Address Calculation in AHB Latest 5 days ago by Colin Campbell||5 replies 11186 views|
|Suggested answer||HTRANS when HREADY is low on the 2nd HCLK after starting the transfer Latest 5 days ago by Colin Campbell||1 replies 275 views|