CoreLink DMC-500

Getting Started

The CoreLink DMC-500 Dynamic Memory Controller provides power-efficient access to LPDDR4 and LPDDR3 memory in mobile, consumer, and embedded designs. The DMC-500 supports dual AXI4 system interfaces and a single DFI 4.0 memory interface.

• Delivering best performance per watt for data transfers from SoC to memory.

• Best combination of features, power, cost, and performance.

• Fast, dual-port AXI4 system interface for transferring data to LPDDR4 and LPDDR3 DRAM memories.

CoreLink DMC-500 key features

System Optimized DMC with support for two AXI4 128-bit wide system interfaces

• One interface for channeling coherent traffic from CoreLink CCI-550 or CoreLink CCI-500 interconnect.
• One interface for supporting real-time or display, or other non-coherent traffic that demands a guaranteed maximum latency.

Single 128-bit wide DFI 4.0 memory interface

• Supporting x16 LPDDR4 up to DDR-4267 and x32 LPDDR3 up to DDR-2133 transfer, dual-DMC channel support for x32 LPDDR4.
• Support for clock gating, dynamic frequency change, and memory low-power modes for optimized power consumption.
• Integration-verified with industry-standard DFI-compatible DDR PHYs.