The CoreLink DMC-500 Dynamic Memory Controller provides power-efficient access to LPDDR4 and LPDDR3 memory in mobile, consumer, and embedded designs. The DMC-500 supports dual AXI4 system interfaces and a single DFI 4.0 memory interface.
- Delivering best performance per watt for data transfers from SoC to memory.
- Best combination of features, power, cost, and performance.
- Fast, dual-port AXI4 system interface for transferring data to LPDDR4 and LPDDR3 DRAM memories.
|Maximum DDR speeds||LPDDR3-2133, LPDDR4-4267|
|Memory width||x32 LPDDR3, x16 LPDDR4, Dual-channel for x32 LPDDR4|
|Chip Selects (per channel)||2|
|QoS||QoS based scheduling algorithm, non-blocking paths to DRAM through CCI|
|Low power||All DRAM power modes are supported and hierarchical clock gating throughout the DMC|
CoreLink DMC-500 key features
System Optimized DMC with support for two AXI4 128-bit wide system interfaces
- One interface for channeling coherent traffic from CoreLink CCI-550 or CoreLink CCI-500 interconnect.
- One interface for supporting real-time or display, or other non-coherent traffic that demands a guaranteed maximum latency.
Single 128-bit wide DFI 4.0 memory interface
- Supporting x16 LPDDR4 up to DDR-4267 and x32 LPDDR3 up to DDR-2133 transfer, dual-DMC channel support for x32 LPDDR4.
- Support for clock gating, dynamic frequency change, and memory low-power modes for optimized power consumption.
- Integration-verified with industry-standard DFI-compatible DDR PHYs.
Integrated TrustZone Controller
- Enabling secure media path protection for Ultra-HD content from Mali multimedia to memory.
- QoS improvements over previous generation reducing average and maximum CPU latency.
- End-to-end QoS optimized with CCI-550 using QoSACCEPT protocol.
CoreLink DMC-500 Characteristics
CoreLink DMC-500 utilizes LPDDR4 which is the most advanced mobile memory technology available today. LPDDR4 lowers power consumption while accessing memory due to a narrower datapath, and improves the speed at which bits are transferred to-and-from memory. System-wide QoS designed and tested with CoreLink CCI-550, CoreLink CCI-500, Cortex-A53 and Cortex-A72 processors, and Mali GPU.
CoreLink DMC-500 Technical Reference Manual
For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.DMC-500 TRM
AMBA 4 ACE Specification
CoreLink DMC-500 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency system designs.AMBA specs
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|Answered||Forum FAQs||0 votes||5557 views||0 replies||Started 8 months ago by Annie||Answer this|
|Answered||Forum FAQs||0 votes||4567 views||0 replies||Started 8 months ago by Annie||Answer this|
|Not answered||Unaligned transfer pattern in AXI4||0 votes||122 views||0 replies||Started yesterday by Supal||Answer this|
|Not answered||AHB - continue the transfer after an error response||0 votes||273 views||0 replies||Started 2 days ago by Joon Hong||Answer this|
|Not answered||Flash Patching in Cortex M7||0 votes||366 views||0 replies||Started 2 days ago by SaiGautamJP||Answer this|
|Answered||HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2)||0 votes||557 views||2 replies||Latest 3 days ago by Tapas||Answer this|
|Answered||Forum FAQs Started 8 months ago by Annie||0 replies 5557 views|
|Answered||Forum FAQs Started 8 months ago by Annie||0 replies 4567 views|
|Not answered||Unaligned transfer pattern in AXI4 Started yesterday by Supal||0 replies 122 views|
|Not answered||AHB - continue the transfer after an error response Started 2 days ago by Joon Hong||0 replies 273 views|
|Not answered||Flash Patching in Cortex M7 Started 2 days ago by SaiGautamJP||0 replies 366 views|
|Answered||HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2) Latest 3 days ago by Tapas||2 replies 557 views|