CoreLink DMC-500

The Arm CoreLink DMC-500 Dynamic Memory Controller

Premium Mobile Cortex A-72 System Diagram.

Getting Started

The CoreLink DMC-500 Dynamic Memory Controller provides power-efficient access to LPDDR4 and LPDDR3 memory in mobile, consumer, and embedded designs. The DMC-500 supports dual AXI4 system interfaces and a single DFI 4.0 memory interface.

  • Delivering best performance per watt for data transfers from SoC to memory.

  • Best combination of features, power, cost, and performance.

  • Fast, dual-port AXI4 system interface for transferring data to LPDDR4 and LPDDR3 DRAM memories.


Specifications

 Features Details
 AMBA interface  AXI4
 System interface
Memory channels 1
 LPDDR4/3  Yes
Maximum DDR speeds  LPDDR3-2133, LPDDR4-4267
 Memory width  x32 LPDDR3, x16 LPDDR4, Dual-channel for x32 LPDDR4
Chip Selects (per channel)  2
 QoS  QoS based scheduling algorithm, non-blocking paths to DRAM through CCI
 Low power  All DRAM power modes are supported and hierarchical clock gating throughout the DMC

DMC-500 Block Diagram.

CoreLink DMC-500 key features

System Optimized DMC with support for two AXI4 128-bit wide system interfaces

  • One interface for channeling coherent traffic from CoreLink CCI-550 or CoreLink CCI-500 interconnect.
  • One interface for supporting real-time or display, or other non-coherent traffic that demands a guaranteed maximum latency.

Single 128-bit wide DFI 4.0 memory interface

  • Supporting x16 LPDDR4 up to DDR-4267 and x32 LPDDR3 up to DDR-2133 transfer, dual-DMC channel support for x32 LPDDR4.
  • Support for clock gating, dynamic frequency change, and memory low-power modes for optimized power consumption.
  • Integration-verified with industry-standard DFI-compatible DDR PHYs.

Integrated TrustZone Controller

  • Enabling secure media path protection for Ultra-HD content from Mali multimedia to memory.

Quality-of-Service (QoS)

  • QoS improvements over previous generation reducing average and maximum CPU latency.
  • End-to-end QoS optimized with CCI-550 using QoSACCEPT protocol.

CoreLink DMC-500 Characteristics

CoreLink DMC-500 utilizes LPDDR4 which is the most advanced mobile memory technology available today. LPDDR4 lowers power consumption while accessing memory due to a narrower datapath, and improves the speed at which bits are transferred to-and-from memory. System-wide QoS designed and tested with CoreLink CCI-550, CoreLink CCI-500, Cortex-A53 and Cortex-A72 processors, and Mali GPU.

  • TRM
  • CoreLink DMC-500 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    DMC-500 TRM
  • A guide on software optimization.
  • AMBA 4 ACE Specification

    CoreLink DMC-500 is built on the AMBA AXI4 specification, targeting high bandwidth, high clock frequency system designs.

    AMBA specs

Resources

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Answered ACE protocol : Eviction and snoop request at same time
  • AMBA
  • l1
  • ACE
  • cache
0 votes 338 views 1 replies Latest 7 days ago by Christopher Tory Answer this
Suggested answer AXI3 write data interleaving with same AWID
  • AMBA
  • AXI
0 votes 401 views 4 replies Latest 7 days ago by mveereshm622 Answer this
Suggested answer AHB revisions from AHB3 to AHB5
  • AMBA
  • AHB
0 votes 151 views 1 replies Latest 8 days ago by Colin Campbell Answer this
Suggested answer Burst termination with BUSY transfer on AHB
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  • AHB
0 votes 129 views 1 replies Latest 8 days ago by Colin Campbell Answer this
Suggested answer Regarding retry response
  • AMBA
  • AHB
0 votes 123 views 1 replies Latest 8 days ago by Colin Campbell Answer this
Suggested answer APB3 Slave responding when PSEL = 0
  • APB
  • AMBA
0 votes 325 views 2 replies Latest 13 days ago by vshankar11 Answer this
Answered ACE protocol : Eviction and snoop request at same time Latest 7 days ago by Christopher Tory 1 replies 338 views
Suggested answer AXI3 write data interleaving with same AWID Latest 7 days ago by mveereshm622 4 replies 401 views
Suggested answer AHB revisions from AHB3 to AHB5 Latest 8 days ago by Colin Campbell 1 replies 151 views
Suggested answer Burst termination with BUSY transfer on AHB Latest 8 days ago by Colin Campbell 1 replies 129 views
Suggested answer Regarding retry response Latest 8 days ago by Colin Campbell 1 replies 123 views
Suggested answer APB3 Slave responding when PSEL = 0 Latest 13 days ago by vshankar11 2 replies 325 views