CoreLink DMC-520

Getting Started

The CoreLink DMC-520 Dynamic Memory Controller provides highest bandwidth with low latency access to DDR4 and DDR3 memory in server, networking, and high-performance computing applications. The DMC-520 provides for full DIMM support along with RAS (Reliability, Availability, and Serviceability) and advanced error correction features that are necessary for these infrastructure applications.

• Delivers best performance with ECC and RAS for data transfers from SoC to high-density memory.

• Best combination of features, power, cost, and performance.

• Fast, single-port CHI.A interface for transferring data to DDR4 and DDR3 DRAM memories.

CoreLink DMC-520 key features

System Optimized DMC with support for single 128-bit wide AMBA 5 CHI system interface

• Integrated TrustZone address space control functionality in system interface to provide secure memory access.

• Includes both standard SECDED ECC and advanced symbol-based ECC for correcting failure of X4 chip.
• DDR3, DDR3L, and DDR4 memories (up to DDR4-3200 speeds) with UDIMM, RDIMM, LRDIMM, and 3DS support.