The CoreLink DMC-520 Dynamic Memory Controller provides highest bandwidth with low latency access to DDR4 and DDR3 memory in server, networking and high-performance computing applications. The DMC-520 provides for full DIMM support along with RAS (Reliability, Availability, and Serviceability) and advanced error correction features that are necessary for these infrastructure applications.
- Delivers best performance with ECC and RAS for data transfers from SoC to high-density memory.
- Best combination of features, power, cost and performance.
- Fast, single-port CHI.A interface for transferring data to DDR4 and DDR3 DRAM memories.
|System data width||128 bit|
|Memory interfaces||Single DFI 3.1 memory interface with configurable 1:1, 1:2, or 1:4 DFI frequency ratio|
|Memory types||DDR3, DDR3(L),and DDR4|
|Memory width||x40/x72 bit DRAM (includes 8 bits of ECC)|
|ECC||SECDED or enhanced symbol-based ECC|
|QoS||QoS based scheduling algorithm, non-blocking paths to DRAM through CCN|
|Low power||All DRAM power modes are supported and hierarchical clock gating throughout the DMC|
CoreLink DMC-520 key features
System Optimized DMC with support for single 128-bit wide AMBA 5 CHI system interface
- Integrated TrustZone address space control functionality in system interface to provide secure memory access.
Support for advanced ECC, RAS,and DIMM capabilities
- Includes both standard SECDED ECC and advanced symbol-based ECC for correcting failure of X4 chip.
- DDR3, DDR3L, and DDR4 memories (up to DDR4-3200 speeds) with UDIMM, RDIMM, LRDIMM, and 3DS support.
- QoS improvements over previous generation reducing average and maximum CPU latency.
- End-to-end QoS optimized with CCN interconnect and Arm v8.x CPUs.
Industry-standard DFI 3.1 Interface
- Proven interoperability with third-party DFI 3.1 compatible DDR PHYs.
CoreLink DMC-520 Characteristics
CoreLink DMC-520 supports DDR4 which is the most advanced infrastructure-class memory technology available today. DDR4 provides the highest bandwidth (up to 25GB/s per channel for DDR4-3200 Mbps) which supporting reliability and low
CoreLink DMC-520 Technical Reference Manual
For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.DMC-520 TRM
AMBA 5 CHI Specification
CoreLink DMC-520 is built on AMBA CHI specification, which is Arm's advanced coherent interconnect for high data transfer bandwidths at GHz and above frequencies.AMBA specs
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|Answered||Forum FAQs||0 votes||2838 views||0 replies||Started 1 months ago by Annie Cracknell||Answer this|
|Answered||Forum FAQs||0 votes||2851 views||0 replies||Started 1 months ago by Annie Cracknell||Answer this|
|Not answered||Does it use a Slow Clock to turn off Main Clock?||0 votes||51 views||0 replies||Started 4 days ago by Ridge Mao||Answer this|
|Answered||Can re-order depth affect functionality of write transaction?||0 votes||564 views||5 replies||Latest 5 days ago by Colin Campbell||Answer this|
|Suggested answer||Alignment Address Calculation in AHB||0 votes||11247 views||5 replies||Latest 7 days ago by Colin Campbell||Answer this|
|Suggested answer||HTRANS when HREADY is low on the 2nd HCLK after starting the transfer||0 votes||297 views||1 replies||Latest 7 days ago by Colin Campbell||Answer this|
|Answered||Forum FAQs Started 1 months ago by Annie Cracknell||0 replies 2838 views|
|Answered||Forum FAQs Started 1 months ago by Annie Cracknell||0 replies 2851 views|
|Not answered||Does it use a Slow Clock to turn off Main Clock? Started 4 days ago by Ridge Mao||0 replies 51 views|
|Answered||Can re-order depth affect functionality of write transaction? Latest 5 days ago by Colin Campbell||5 replies 564 views|
|Suggested answer||Alignment Address Calculation in AHB Latest 7 days ago by Colin Campbell||5 replies 11247 views|
|Suggested answer||HTRANS when HREADY is low on the 2nd HCLK after starting the transfer Latest 7 days ago by Colin Campbell||1 replies 297 views|