CoreLink DMC-520

Getting Started

The CoreLink DMC-520 Dynamic Memory Controller provides highest bandwidth with low latency access to DDR4 and DDR3 memory in server, networking, and high-performance computing applications. The DMC-520 provides for full DIMM support along with RAS (Reliability, Availability, and Serviceability) and advanced error correction features that are necessary for these infrastructure applications.

• Delivers best performance with ECC and RAS for data transfers from SoC to high-density memory.
• Best combination of features, power, cost, and performance.
• Fast, single-port CHI.A interface for transferring data to DDR4 and DDR3 DRAM memories.

Specifications

Quality-of-Service (QoS)

• QoS improvements over previous generation reducing average and maximum CPU latency.
• End-to-end QoS optimized with CCN interconnect and Arm v8.x CPUs.

Industry-standard DFI 3.1 Interface

• Proven interoperability with third-party DFI 3.1 compatible DDR PHYs.

CoreLink DMC-520 Characteristics

CoreLink DMC-520 supports DDR4 which is the most advanced infrastructure-class memory technology available today. DDR4 provides the highest bandwidth (up to 25GB/s per channel for DDR4-3200 Mbps) which supporting reliability and low power features necessary for high-end systems deployment. System-wide QoS for DMC-520 designed and tested with CoreLink CCN Family, Cortex A53, and Cortex A72 processors.

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