CoreLink DMC-620

In-built memory access security for your SoC

CoreLink DMC-620 provides integrated Arm TrustZone Address Space Control (TZASC) enabling programmable memory access protection for different masters in the SoC. Integration of TZASC functionality within the memory controller saves gate area and latency cycles as memory access rights are evaluated in parallel with other memory controller functions.

CoreLink DMC-620 supports multiple DIMM standards - UDIMM, RDIMM, and LRDIMM. Moreover, it has extended virtual rank support to enable addressing of very high-density 2H, 4H, or 8H 3DS DRAM devices. With this support, a single channel of CoreLink DMC-620 can address up to 1TB of DRAM memory, providing system designers with sufficient headroom for growing the DRAM footprint of their high-end systems.

CoreLink DMC-620 integrates with CoreLink CMN-600 supporting the latest Arm 64-bit processors and high frequency AMBA 5 CHI (Coherent Hub Interface). The fast, non-blocking CHI port on CoreLink DMC-620 ensures access to memory for multiple, competing masters guaranteeing that there are no unexpected blocks to flow of data to and from memory. 

CoreLink DMC-620 has the best combination of features, power, cost, and performance. It is built on top of a family of silicon-proven DMC products that guarantee interoperability with any DFI-compliant DDR PHY and with JEDEC-compliant DDR4, DDR3, and DDR3L DRAM memory. Deploying CoreLink DMC-620 in your SoC delivers considering cost savings and helps to accelerate your tape-out. These cost savings come from not only the development itself but also from multiple person-years that Arm spends in optimizing, tuning, and validating performance and interoperability in a real sub-system.