The Arm CoreLink DMC-620 Dynamic Memory Controller is designed to provide an optimal memory access solution for SoCs deployed in infrastructure applications such as servers, High-Performance Computing (HPC), and networking.
- Delivers best performance with ECC and RAS for data transfers from SoC to high-density DRAM memory.
- Best combination of features, power, cost, and performance.
- Fast, single-port CHI.B interface for transferring data from CMN-600 to DDR4/3 DRAM memories.
|System interface||x for direct connection to CCN-5xx or CMN-600 products using AMBA 5 CHI|
|System data width||256-bit or 128-bit|
|Memory interfaces||Single interface per channel, which is connected to PHY with DFI 4.0|
|Memory type||DDRS, DDR3(L), and DDR4 with support for UDIMM, RDIMM, LRDIMM, and NVDIMM-N|
|Maximum DDR speeds||Up to DDR4-3200 Mbps|
|Memory width||x72 or x40 bit (including 8-bit ECC)|
|ECC||SECDED or symbol-based ECC|
|Chip Selects (per channel)||8|
|QoS||QoS based scheduling algorithm, non-blocking paths to DRAM through CMN|
|Latency||QoS mechanisms that ensure critical masters can achieve minimum latency|
|Low power||All DRAM power modes are supported and hierarchical clock gating throughout the DMC|
CoreLink DMC-620 key features
Lowest memory latency with highest bandwidth utilization delivering QoS with RAS
The Arm CoreLink DMC-620 delivers best performance for data transfers from SoC to high-density DRAM memory
- Delivers up to 95% of maximum memory bandwidth utilization
- Reduces static pipeline latency by up to 50% from previous generation CoreLink DMC-520
- Provides optimized performance and end-to-end QoS with CoreLink CMN-600
Reliability, Availability, and Serviceability (RAS) is a key requirement for SoCs deployed in infrastructure applications. The CoreLink DMC-620 offers support for sophisticated RAS features such as end-to-end data parity protection, corrected data write-back, retry on uncorrectable ECC errors, memory scrubbing, and standardized error reporting. It supports both the standard SECDED (Single Error Correct Multiple Error Detect) and advanced symbol-based ECC for correcting complete failure of a x4 memory device.
In-built memory access security for your SoC
CoreLink DMC-620 provides integrated Arm TrustZone Address Space Control (TZASC) enabling programmable memory access protection for different masters in the SoC. Integration of TZASC functionality within the memory controller saves gate area and latency cycles as memory access rights are evaluated in parallel with other memory controller functions.
Dual-in-line-memory module (DIMM) and high-density DRAM support
CoreLink DMC-620 supports multiple DIMM standards - UDIMM, RDIMM, and LRDIMM. Moreover, it has extended virtual rank support to enable addressing of very high-density 2H, 4H, or 8H 3DS DRAM devices. With this support, a single channel of CoreLink DMC-620 can address up to 1TB of DRAM memory, providing system designers with sufficient headroom for growing the DRAM footprint of their high-end systems.
Fast, single-port AMBA 5 CHI interface
CoreLink DMC-620 integrates with CoreLink CMN-600 supporting the latest Arm 64-bit processors and high frequency AMBA 5 CHI (Coherent Hub Interface). The fast, non-blocking CHI port on CoreLink DMC-620 ensures access to memory for multiple, competing masters guaranteeing that there are no unexpected blocks to flow of data to and from memory.
Reduce development cost and improve time-to-market
CoreLink DMC-620 has the best combination of features, power, cost, and performance. It is built on top of a family of silicon-proven DMC products that guarantee interoperability with any DFI-compliant DDR PHY and with JEDEC-compliant DDR4, DDR3, and DDR3L DRAM memory. Deploying CoreLink DMC-620 in your SoC delivers considering cost savings and helps to accelerate your tape-out. These cost savings come from not only the development itself but also from multiple person-years that Arm spends in optimizing, tuning, and validating performance and interoperability in a real sub-system.
CoreLink DMC-620 Technical Reference Manual
For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.DMC-620 TRM
AMBA 5 CHI Specification
CoreLink DMC-620 is built on AMBA CHI specification, which is Arm's advanced coherent interconnect for high data transfer bandwidths at GHz and above frequencies.AMBA specs
Get support with Arm training courses and design reviews. You can also open a support case or manage existing cases.Arm training courses Arm Design Reviews Open a support case
|Answered||Forum FAQs||0 votes||5193 views||0 replies||Started 8 months ago by Annie||Answer this|
|Answered||Forum FAQs||0 votes||4552 views||0 replies||Started 8 months ago by Annie||Answer this|
|Suggested answer||How to calculate AXI interleave depth and reorder depth.||0 votes||3714 views||3 replies||Latest 2 days ago by Koalassy||Answer this|
|Answered||One master to two slave transfer (back to back) behavior for address A (slave1) and address B (slave2)||0 votes||168 views||2 replies||Latest 2 days ago by Tapas||Answer this|
|Suggested answer||Error with Keil RTX5 tutorial||0 votes||1057 views||8 replies||Latest 4 days ago by Kevin B||Answer this|
|Answered||Is __CC_ARM not defined in the MDK Eval Version?||0 votes||726 views||12 replies||Latest 4 days ago by Grant B||Answer this|
|Answered||Forum FAQs Started 8 months ago by Annie||0 replies 5193 views|
|Answered||Forum FAQs Started 8 months ago by Annie||0 replies 4552 views|
|Suggested answer||How to calculate AXI interleave depth and reorder depth. Latest 2 days ago by Koalassy||3 replies 3714 views|
|Answered||One master to two slave transfer (back to back) behavior for address A (slave1) and address B (slave2) Latest 2 days ago by Tapas||2 replies 168 views|
|Suggested answer||Error with Keil RTX5 tutorial Latest 4 days ago by Kevin B||8 replies 1057 views|
|Answered||Is __CC_ARM not defined in the MDK Eval Version? Latest 4 days ago by Grant B||12 replies 726 views|