Getting Started

Optimized and efficient access to the DRAM is critical to the performance of any chip. As the number of processing elements on a chip increases, so does the demand for data. With DRAM technology transitioning to DDR4 for infrastructure and LPDDR4 for mobile and consumer applications, not only does the frequency of DRAM operation increase significantly, but also the complexity of making the best use of the DRAM bandwidth to deliver high Quality of Service (QoS) at low power, increases. Managing the differing demands of multiple processing elements while delivering maximum DRAM bandwidth is the primary challenge addressed by the Dynamic Memory Controller (DMC).

The Dynamic Memory Controller family

CoreLink DMC-500 Dynamic Memory Controller

CoreLink DMC-500 Dynamic Memory Controller

  • Specifically designed for low power operation in mobile, consumer and embedded applications that utilize LPDDR4 and LPDDR3 memories
  • Optimized for best memory bandwidth at low latencies with Arm CoreLink CCI and NIC




CoreLink DMC-520 Dynamic Memory Controller

CoreLink DMC-520 Dynamic Memory Controller

  • Targeted at applications in server, networking and high-performance computing, using DDR4 and DDR3 memories
  • Supports enterprise-class requirements for high-density DIMMs, error correction codes and reliability with ease-of-use Optimized for highest performance with the CoreLink CCN family


DMC-620

CoreLink DMC-620 Dynamic Memory Controller

  • Builds on top of DMC-520 features to provide the best performance with RAS and end-to-end QoS support with CoreLink CMN-600.
  • Reduces static pipeline latency by up to 50% compared to DMC-520. Expands support for 3DS DRAM with extended virtual rank support.
  • Improves memory access latency for Arm Cortex v8-A processors significantly under common operating conditions.


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Suggested answer Hard fault handler problem - Cortex-M0+
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Suggested answer Making ONVIF conformant surveillance camera with STM32H743.
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Suggested answer Hard fault handler problem - Cortex-M0+ Latest 4 days ago by Clonimus74 4 replies 1238 views
Suggested answer After first execution control goes to task 2 but i want him to go to task1 what i suppose to do here? Latest 8 days ago by fixxxer 1 replies 566 views
Suggested answer Is there any extra parameter needed to start networking on FVP_MPS2_M7 simulator? Latest 8 days ago by fixxxer 1 replies 1275 views
Suggested answer L1 cache BW Latest 8 days ago by fixxxer 2 replies 843 views
Suggested answer Making ONVIF conformant surveillance camera with STM32H743. Latest 10 days ago by ibrahim1236 5 replies 1220 views
Suggested answer Which ARM board will be most suitable? Latest 11 days ago by Dharmalingam.K 3 replies 2062 views