Getting Started

Optimized and efficient access to the DRAM is critical to the performance of any chip. As the number of processing elements on a chip increases, so does the demand for data. With DRAM technology transitioning to DDR4 for infrastructure and LPDDR4 for mobile and consumer applications, not only does the frequency of DRAM operation increase significantly, but also the complexity of making the best use of the DRAM bandwidth to deliver high Quality of Service (QoS) at low power, increases. Managing the differing demands of multiple processing elements while delivering maximum DRAM bandwidth is the primary challenge addressed by the Dynamic Memory Controller (DMC).

The Dynamic Memory Controller family

CoreLink DMC-500 Dynamic Memory Controller

CoreLink DMC-500 Dynamic Memory Controller

  • Specifically designed for low power operation in mobile, consumer and embedded applications that utilize LPDDR4 and LPDDR3 memories
  • Optimized for best memory bandwidth at low latencies with Arm CoreLink CCI and NIC




CoreLink DMC-520 Dynamic Memory Controller

CoreLink DMC-520 Dynamic Memory Controller

  • Targeted at applications in server, networking and high-performance computing, using DDR4 and DDR3 memories
  • Supports enterprise-class requirements for high-density DIMMs, error correction codes and reliability with ease-of-use Optimized for highest performance with the CoreLink CCN family


DMC-620

CoreLink DMC-620 Dynamic Memory Controller

  • Builds on top of DMC-520 features to provide the best performance with RAS and end-to-end QoS support with CoreLink CMN-600.
  • Reduces static pipeline latency by up to 50% compared to DMC-520. Expands support for 3DS DRAM with extended virtual rank support.
  • Improves memory access latency for Arm Cortex v8-A processors significantly under common operating conditions.


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Arm support

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Community Blogs

Community Forums

Not answered Handshaking for the write data channel 0 votes 10 views 0 replies Started 6 hours ago by Ravi V. Answer this
Not answered Looking for manufacturer to produce our motherboard design 0 votes 31 views 0 replies Started 12 hours ago by Fran Saez Answer this
Suggested answer BUSY transfer and WAIT state both are using the same time ,How to perform the AHB?
  • AHB
0 votes 3710 views 2 replies Latest yesterday by Mukul_Prajapati Answer this
Answered Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior
  • AMBA
  • ACE
  • ACE 5
  • interconnect
  • AMBA 5
0 votes 6871 views 6 replies Latest 2 days ago by AlexR Answer this
Suggested answer AXI3 locked access
  • AMBA
  • AXI
0 votes 3089 views 3 replies Latest 3 days ago by Colin Campbell Answer this
Answered Difference btw AXI3 and AXI4
  • AMBA
  • AXI3
  • AXI4
  • Interface
0 votes 11071 views 6 replies Latest 3 days ago by Colin Campbell Answer this
Not answered Handshaking for the write data channel Started 6 hours ago by Ravi V. 0 replies 10 views
Not answered Looking for manufacturer to produce our motherboard design Started 12 hours ago by Fran Saez 0 replies 31 views
Suggested answer BUSY transfer and WAIT state both are using the same time ,How to perform the AHB? Latest yesterday by Mukul_Prajapati 2 replies 3710 views
Answered Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior Latest 2 days ago by AlexR 6 replies 6871 views
Suggested answer AXI3 locked access Latest 3 days ago by Colin Campbell 3 replies 3089 views
Answered Difference btw AXI3 and AXI4 Latest 3 days ago by Colin Campbell 6 replies 11071 views