Overview

The Arm CoreLink System Controllers

Arm CoreLink System Controllers orchestrate critical AMBA system tasks such as hardware virtualization support, interrupt management, L3 cache operation, DMA, TrustZone security and peripheral operation. Designed for optimal compatibility with Arm processors and Multimedia IP, they are the natural complements to the System IP Interconnect and Memory Controller product lines. 

Generic Interrupt Controller (GIC)

 

  • Supports interrupt detection, prioritization, re-distribution and virtualization
  • Handles Private Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI), Software Generated Interrupts (SGI) and Locality Peripheral Interrupts (LPI)
  • GIC-500 also supports message-based interrupts such as PCI Express MSI/MSI-X interrupts, and Interrupt Translation Services for ID translation and core migration

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System Memory Management Unit

 

  • Provides same view of memory to IO peripheral devices as CPU using stage1 and/or stage2 virtual to physical address translation
  • Enforces memory protection and access schematic while extending memory virtualization services that match those provided by the main application processor to ensure consistent security across the SoC
  • The CoreLink MMU-600 has a stage 2 protection mechanism which enables TrustZone Media Protection v2 (TZMP2) with master side filtering

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Other System Controllers

 

  •  Controllers perform critical system tasks such as TrustZone Security, DMA, Level 2 Cache and IO Peripherals' operation

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Use Cases

System Controllers are used for many functions within an SoC, including:

Virtualization

Virtualization is the ability of a system to support multiple virtual machines each running its own guest operating system with its own private access to memory and IO peripherals without any interference whatsoever from the others. Arm's SMMU enables hardware virtualization by performing stage1 and/or stage2 address translation for IO devices, thereby providing them with the same view of memory as the CPU/GPU. 


Memory Mapping

Another interesting use case of SMMU is to perform memory mapping to enable a programmable view of memory for IO peripherals. As an example, SMMU supports scatter-gather operations whereby an IO peripheral can access disjoint locations of physical memory as a single contiguous block of virtual memory due to the SMMU translation. This results in improved utilization of memory while ensuring that the IO peripheral performance is not affected. 


Cache Control

CPU to off-chip memory communication has become the performance bottleneck in many SoCs. Level 2 Cache Controllers improve CPU performance by keeping memory access on-chip with a typical latency 10-25% of accessing the data off-chip. At the same time, the reduced CPU demands on the off-chip memory bandwidth free up that resource for other masters. Level 2 Cache Controllers also contribute significantly to power efficiency as on-chip accesses are typically an order of magnitude lower in power versus going off-chip. Typically these are embedded inside the CPU or delivered as standalone components optimized to match the processor requirements and integrate easily into the AMBA interconnect.


Interrupt Management & Translation

Arm GICs perform the key function of interrupt management and translation. Management functions include detection, masking, prioritization and routing of interrupts to the appropriate cores. Interrupt Translation Service (ITS) modules in the GIC perform the task of device isolation and ID translation for incoming message-based interrupts, thereby enabling virtual machines to program peripherals directly.


Security

Arm's TrustZone security platform enables hardware-based secure access to regions of both off-chip memory and on-chip SRAM. The memory space is divided into a configurable number of regions each with its own access permissions. This setup ensures that malicious software cannot compromise system operation by latching onto data or code it shouldn't have access to. 


Direct Access to Memory

Arm's CoreLink DMA controllers perform critical functions of moving streams of data between a peripheral and memory without overloading the CPU. Software programs typically write the data transfer instructions to memory and trigger the DMA engine which then takes over and performs the data move without incurring any additional overhead on the CPU.

 

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Not answered SMMUv2 - Arm Corelink-MMU500 on Xilinx Zynq Ultrascale+
  • CoreLink MMU-500 System Memory Management Unit
  • Armv8-A
  • SMMUv2
0 votes 35 views 0 replies Started yesterday by Ciro Donnarumma Answer this
Suggested answer boundary concept
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Suggested answer Amba Adaptive Traffic Profiles question
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0 votes 130 views 1 replies Latest 8 days ago by Matteo Maria Andreozzi Answer this
Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?
  • AXI
0 votes 209 views 2 replies Latest 9 days ago by Zax Answer this
Suggested answer Assertion for Multiple Transfer on APB Bus
  • APB
  • AMBA
  • Bus Architecture
0 votes 145 views 2 replies Latest 9 days ago by Rakesh Venkatesan Answer this
Not answered SMMUv2 - Arm Corelink-MMU500 on Xilinx Zynq Ultrascale+ Started yesterday by Ciro Donnarumma 0 replies 35 views
Suggested answer boundary concept Latest 3 days ago by harrykayn 3 replies 333 views
Suggested answer State Machine for AHB-Lite Protocol Latest 5 days ago by Colin Campbell 3 replies 200 views
Suggested answer Amba Adaptive Traffic Profiles question Latest 8 days ago by Matteo Maria Andreozzi 1 replies 130 views
Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst? Latest 9 days ago by Zax 2 replies 209 views
Suggested answer Assertion for Multiple Transfer on APB Bus Latest 9 days ago by Rakesh Venkatesan 2 replies 145 views