Arm CoreLink System Controllers orchestrate critical AMBA system tasks such as hardware virtualization support, interrupt management, L3 cache operation, DMA, TrustZone security and peripheral operation. Designed for optimal compatibility with Arm processors and Multimedia IP, they are the natural complements to the System IP Interconnect and Memory Controller product lines.
- Supports interrupt detection, prioritization, re-distribution and virtualization
- Handles Private Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI), Software Generated Interrupts (SGI) and Locality Peripheral Interrupts (LPI)
- GIC-500 also supports message-based interrupts such as PCI Express MSI/MSI-X interrupts, and Interrupt Translation Services for ID translation and core migration
- Provides same view of memory to IO peripheral devices as CPU using stage1 and/or stage2 virtual to physical address translation
- Enforces memory protection and access schematic while extending memory virtualization services that match those provided by the main application processor to ensure consistent security across the SoC
- The CoreLink MMU-600 has a stage 2 protection mechanism which enables TrustZone Media Protection v2 (TZMP2) with master side filtering
System Controllers are used for many functions within an SoC, including:
Virtualization is the ability of a system to support multiple virtual machines each running its own guest operating system with its own private access to memory and IO peripherals without any interference whatsoever from the others. Arm's SMMU enables hardware virtualization by performing stage1 and/or stage2 address translation for IO devices, thereby providing them with the same view of memory as the CPU/GPU.
Another interesting use case of SMMU is to perform memory mapping to enable a programmable view of memory for IO peripherals. As an example, SMMU supports scatter-gather operations whereby an IO peripheral can access disjoint locations of physical memory as a single contiguous block of virtual memory due to the SMMU translation. This results in improved utilization of memory while ensuring that the IO peripheral performance is not affected.
CPU to off-chip memory communication has become the performance bottleneck in many SoCs. Level 2 Cache Controllers improve CPU performance by keeping memory access on-chip with a typical latency 10-25% of accessing the data off-chip. At the same time, the reduced CPU demands on the off-chip memory bandwidth free up that resource for other masters. Level 2 Cache Controllers also contribute significantly to power efficiency as on-chip accesses are typically an order of magnitude lower in power versus going off-chip. Typically these are embedded inside the CPU or delivered as standalone components optimized to match the processor requirements and integrate easily into the AMBA interconnect.
Interrupt Management & Translation
Arm GICs perform the key function of interrupt management and translation. Management functions include detection, masking, prioritization and routing of interrupts to the appropriate cores. Interrupt Translation Service (ITS) modules in the GIC perform the task of device isolation and ID translation for incoming message-based interrupts, thereby enabling virtual machines to program peripherals directly.
Arm's TrustZone security platform enables hardware-based secure access to regions of both off-chip memory and on-chip SRAM. The memory space is divided into a configurable number of regions each with its own access permissions. This setup ensures that malicious software cannot compromise system operation by latching onto data or code it shouldn't have access to.
Direct Access to Memory
Arm's CoreLink DMA controllers perform critical functions of moving streams of data between a peripheral and memory without overloading the CPU. Software programs typically write the data transfer instructions to memory and trigger the DMA engine which then takes over and performs the data move without incurring any additional overhead on the CPU.
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|Not answered||what action will be performed by the master based on the read and write responce in axi 4? Started 5 hours ago by Hem Patel||0 replies 14 views|
|Answered||ACE protocol : Eviction and snoop request at same time Latest 8 days ago by Christopher Tory||1 replies 344 views|
|Suggested answer||AXI3 write data interleaving with same AWID Latest 8 days ago by mveereshm622||4 replies 411 views|
|Suggested answer||AHB revisions from AHB3 to AHB5 Latest 9 days ago by Colin Campbell||1 replies 153 views|
|Suggested answer||Burst termination with BUSY transfer on AHB Latest 9 days ago by Colin Campbell||1 replies 131 views|
|Suggested answer||Regarding retry response Latest 9 days ago by Colin Campbell||1 replies 124 views|