Arm CoreLink System Controllers orchestrate critical AMBA system tasks such as hardware virtualization support, interrupt management, L3 cache operation, DMA, TrustZone security and peripheral operation. Designed for optimal compatibility with Arm processors and Multimedia IP, they are the natural complements to the System IP Interconnect and Memory Controller product lines.
System Controllers are used for many functions within an SoC, including:
Virtualization is the ability of a system to support multiple virtual machines each running its own guest operating system with its own private access to memory and IO peripherals without any interference whatsoever from the others. Arm's SMMU enables hardware virtualization by performing stage1 and/or stage2 address translation for IO devices, thereby providing them with the same view of memory as the CPU/GPU.
Another interesting use case of SMMU is to perform memory mapping to enable a programmable view of memory for IO peripherals. As an example, SMMU supports scatter-gather operations whereby an IO peripheral can access disjoint locations of physical memory as a single contiguous block of virtual memory due to the SMMU translation. This results in improved utilization of memory while ensuring that the IO peripheral performance is not affected.
CPU to off-chip memory communication has become the performance bottleneck in many SoCs. Level 2 Cache Controllers improve CPU performance by keeping memory access on-chip with a typical latency 10-25% of accessing the data off-chip. At the same time, the reduced CPU demands on the off-chip memory bandwidth free up that resource for other masters. Level 2 Cache Controllers also contribute significantly to power efficiency as on-chip accesses are typically an order of magnitude lower in power versus going off-chip. Typically these are embedded inside the CPU or delivered as standalone components optimized to match the processor requirements and integrate easily into the AMBA interconnect.
Interrupt Management & Translation
Arm GICs perform the key function of interrupt management and translation. Management functions include detection, masking, prioritization and routing of interrupts to the appropriate cores. Interrupt Translation Service (ITS) modules in the GIC perform the task of device isolation and ID translation for incoming message-based interrupts, thereby enabling virtual machines to program peripherals directly.
Arm's TrustZone security platform enables hardware-based secure access to regions of both off-chip memory and on-chip SRAM. The memory space is divided into a configurable number of regions each with its own access permissions. This setup ensures that malicious software cannot compromise system operation by latching onto data or code it shouldn't have access to.
Direct Access to Memory
Arm's CoreLink DMA controllers perform critical functions of moving streams of data between a peripheral and memory without overloading the CPU. Software programs typically write the data transfer instructions to memory and trigger the DMA engine which then takes over and performs the data move without incurring any additional overhead on the CPU.
Get support with Arm Training courses and design reviews. You can also open a support case or manage existing cases.
|Suggested answer||After first execution control goes to task 2 but i want him to go to task1 what i suppose to do here?||0 votes||289 views||1 replies||Latest yesterday by fixxxer||Answer this|
|Suggested answer||Is there any extra parameter needed to start networking on FVP_MPS2_M7 simulator?||0 votes||1003 views||1 replies||Latest 2 days ago by fixxxer||Answer this|
|Suggested answer||L1 cache BW||0 votes||554 views||2 replies||Latest 2 days ago by fixxxer||Answer this|
|Suggested answer||Making ONVIF conformant surveillance camera with STM32H743.||0 votes||912 views||5 replies||Latest 4 days ago by ibrahim1236||Answer this|
|Suggested answer||Which ARM board will be most suitable?||0 votes||1766 views||3 replies||Latest 5 days ago by Dharmalingam.K||Answer this|
|Suggested answer||In AXI Why there is a read response in each data transfer?||0 votes||5507 views||4 replies||Latest 5 days ago by Jenniferl||Answer this|
|Suggested answer||After first execution control goes to task 2 but i want him to go to task1 what i suppose to do here? Latest yesterday by fixxxer||1 replies 289 views|
|Suggested answer||Is there any extra parameter needed to start networking on FVP_MPS2_M7 simulator? Latest 2 days ago by fixxxer||1 replies 1003 views|
|Suggested answer||L1 cache BW Latest 2 days ago by fixxxer||2 replies 554 views|
|Suggested answer||Making ONVIF conformant surveillance camera with STM32H743. Latest 4 days ago by ibrahim1236||5 replies 912 views|
|Suggested answer||Which ARM board will be most suitable? Latest 5 days ago by Dharmalingam.K||3 replies 1766 views|
|Suggested answer||In AXI Why there is a read response in each data transfer? Latest 5 days ago by Jenniferl||4 replies 5507 views|