Arm CoreLink System Controllers orchestrate critical AMBA system tasks such as hardware virtualization support, interrupt management, L3 cache operation, DMA, TrustZone security and peripheral operation. Designed for optimal compatibility with Arm processors and Multimedia IP, they are the natural complements to the System IP Interconnect and Memory Controller product lines.
System Controllers are used for many functions within an SoC, including:
Virtualization is the ability of a system to support multiple virtual machines each running its own guest operating system with its own private access to memory and IO peripherals without any interference whatsoever from the others. Arm's SMMU enables hardware virtualization by performing stage1 and/or stage2 address translation for IO devices, thereby providing them with the same view of memory as the CPU/GPU.
Another interesting use case of SMMU is to perform memory mapping to enable a programmable view of memory for IO peripherals. As an example, SMMU supports scatter-gather operations whereby an IO peripheral can access disjoint locations of physical memory as a single contiguous block of virtual memory due to the SMMU translation. This results in improved utilization of memory while ensuring that the IO peripheral performance is not affected.
CPU to off-chip memory communication has become the performance bottleneck in many SoCs. Level 2 Cache Controllers improve CPU performance by keeping memory access on-chip with a typical latency 10-25% of accessing the data off-chip. At the same time, the reduced CPU demands on the off-chip memory bandwidth free up that resource for other masters. Level 2 Cache Controllers also contribute significantly to power efficiency as on-chip accesses are typically an order of magnitude lower in power versus going off-chip. Typically these are embedded inside the CPU or delivered as standalone components optimized to match the processor requirements and integrate easily into the AMBA interconnect.
Interrupt Management & Translation
Arm GICs perform the key function of interrupt management and translation. Management functions include detection, masking, prioritization and routing of interrupts to the appropriate cores. Interrupt Translation Service (ITS) modules in the GIC perform the task of device isolation and ID translation for incoming message-based interrupts, thereby enabling virtual machines to program peripherals directly.
Arm's TrustZone security platform enables hardware-based secure access to regions of both off-chip memory and on-chip SRAM. The memory space is divided into a configurable number of regions each with its own access permissions. This setup ensures that malicious software cannot compromise system operation by latching onto data or code it shouldn't have access to.
Direct Access to Memory
Arm's CoreLink DMA controllers perform critical functions of moving streams of data between a peripheral and memory without overloading the CPU. Software programs typically write the data transfer instructions to memory and trigger the DMA engine which then takes over and performs the data move without incurring any additional overhead on the CPU.
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|Answered||Forum FAQs||0 votes||2824 views||0 replies||Started 1 months ago by Annie Cracknell||Answer this|
|Answered||Forum FAQs||0 votes||2839 views||0 replies||Started 1 months ago by Annie Cracknell||Answer this|
|Not answered||Does it use a Slow Clock to turn off Main Clock?||0 votes||35 views||0 replies||Started 2 days ago by Ridge Mao||Answer this|
|Answered||Can re-order depth affect functionality of write transaction?||0 votes||520 views||5 replies||Latest 3 days ago by Colin Campbell||Answer this|
|Suggested answer||Alignment Address Calculation in AHB||0 votes||11178 views||5 replies||Latest 5 days ago by Colin Campbell||Answer this|
|Suggested answer||HTRANS when HREADY is low on the 2nd HCLK after starting the transfer||0 votes||271 views||1 replies||Latest 5 days ago by Colin Campbell||Answer this|
|Answered||Forum FAQs Started 1 months ago by Annie Cracknell||0 replies 2824 views|
|Answered||Forum FAQs Started 1 months ago by Annie Cracknell||0 replies 2839 views|
|Not answered||Does it use a Slow Clock to turn off Main Clock? Started 2 days ago by Ridge Mao||0 replies 35 views|
|Answered||Can re-order depth affect functionality of write transaction? Latest 3 days ago by Colin Campbell||5 replies 520 views|
|Suggested answer||Alignment Address Calculation in AHB Latest 5 days ago by Colin Campbell||5 replies 11178 views|
|Suggested answer||HTRANS when HREADY is low on the 2nd HCLK after starting the transfer Latest 5 days ago by Colin Campbell||1 replies 271 views|