AMBA cache controllers are a collection of controller IP that Arm offers to enhance the system performance of microcontrollers. These controllers are low-power and optimized to perform critical tasks within the AMBA system. Designed for compatibility with Arm Cortex, Mali multimedia, and CoreLink system IP, they are the natural complement to interconnect and memory controllers.

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CoreLink L2C-310 level 2 cache controller | CoreLink AHB Cache | CoreLink AHB Flash Cache | SSE-200 instruction Cache


CoreLink L2C-310 level 2 cache controller

Processor to off-chip memory communication has become the performance bottleneck in many SoCs. Level 2 cache controllers improve processor performance by keeping memory access on-chip with a typical latency between 10-25% for accessing the data off-chip. At the same time, the reduced processor demands on the off-chip memory bandwidth free up that resource for other masters.

Level 2 cache controllers also contribute significantly to power efficiency because on-chip accesses are typically lower in power when compared to going off-chip. CoreLink level 2 cache controllers can be embedded in the processor, or delivered as standalone components. The level 2 cache controllers are designed alongside the processor to match the processor requirements and easily integrate into AMBA AXI or AHB interconnects.

The CoreLink L2C-310 cache controller is a high-performance, AXI level 2 cache controller that is designed and optimized to address Arm processors that have an AXI system interface. The processors include:

View the L2C-310 Technical Reference Manual:

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CoreLink AHB Cache

Memory sizes required for applications are increasing for both on and off-chip memories across various technologies such as SRAM, PSRAM, Flash and DRAM. Typically, a larger size has a direct implication on the memory access latency. Slower memories and higher latency memories could have a significant impact on the system performance of AHB-based processors. As the capabilities of microcontrollers are set to increase over time, a solution is required to store frequently used data, and ensure system performance does not reduce.

The Arm CoreLink AHB Cache has been designed to reduce the impact of high system memory latency. It is a versatile cache for data and code. Depending on the application, when the AHB Cache has many cache hits, it lowers an SoCs power and overall memory access latency due to reduced system memory access.

CoreLink AHB Cache

Other key features include:

  • 4-way set associative
  • Zero bus wait state when the access is a cache hit.
  • Cache size of 2kB to 64kB
  • Cache line size of 32B
  • Configurable Write-Through or write-back policy
  • Pseudo-random replacement policy
  • Support for hit and miss counters.
  • Supports Q-Channel based power control.
  • Supports software cache maintenance operations

CoreLink AHB Cache can be added to a system in several configurations for different IoT and embedded use cases. It supports 32-bit AMBA 5 AHB with TrustZone for Armv8-M support. It is compatible with the following processor IP:

View the CoreLink AHB Cache Technical Reference Manual:

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CoreLink AHB Flash Cache

The CoreLink AHB Flash Cache is an instruction cache that is instantiated between the bus interconnect and the eFlash controller. It is designed to improve power efficiency in Cortex-M-based designs, and improve code fetching performance in a system.

The cache is for on-chip embedded Flash (eFlash) and is optimized for fetching Cortex-M processor instructions directly from an eFlash. Other key features include:

  • 128-bit data interface for the master and 32-bit data interface for the slave
  • 2-way associative or direct mapped
  • Four words per line (16B cache line size)
  • Optional support for configurable hit and miss counters.

CoreLink AHB Flash Cache is a part of the Arm Corstone-102, Corstone-201, Corstone-300, and Corstone-700.

View the AHB Flash Cache Technical Reference Manual:

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SSE-200 Instruction Cache

The Instruction Cache integrated in the SSE-200 subsystem is designed to reduce the code access fetches that are targeting the flash memory, to improve the flash and power of the subsystem. The Instruction Cache also reduces the overall latency of code access.

The SSE-200 Instruction Cache is optimized for systems based on the Cortex-M33 processor, supporting TrustZone for Armv8-M. It is a part of Arm Corstone-201. Other key features include:

  • 2-way set associative
  • 16-Byte cache lines
  • Configurable size
  • Configuration interface local to each processor
  • Supports uncached bypass operation

View the Instruction Cache technical reference manual

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Not answered what is the extra FPGA utilization of debug/trace features in Cortex-M3 Xilinx edition Started 10 hours ago by yonathan 0 replies 31 views
Suggested answer -print-libgcc-file-name gives thumb while -marm is used Latest 12 hours ago by 42Bastian Schick 1 replies 311 views
Suggested answer run standalone software in user mode Latest 12 hours ago by 42Bastian Schick 1 replies 276 views
Suggested answer data cached during level-2 page walk Latest yesterday by XNoOp 2 replies 592 views
Answered Can I change the frequency of the generic timer in armv8? Latest yesterday by Zili 2 replies 336 views
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