Getting Started

AMBA system controllers are a collection of controller IP that Arm offers. These controllers are for Direct Memory Access (DMA), Level 2 Cache, and peripherals. These controllers are low-power, high-performance IP cores that perform critical tasks within the AMBA system. Designed for optimal compatibility with Arm Cortex, Mali multimedia, and CoreLink System IP, they are the natural complement to interconnect and memory controllers.


CoreLink L2C-310 level 2 cache controller

Processor to off-chip memory communication has become the performance bottleneck in many SoCs. Level 2 cache controllers improve processor performance by keeping memory access on-chip with a typical latency 10-25% of accessing the data off-chip. At the same time, the reduced processor demands on the off-chip memory bandwidth free up that resource for other masters. Level 2 cache controllers also contribute significantly to power efficiency because on-chip accesses are typically an order of magnitude lower in power when compared to going off-chip. CoreLink level 2 cache controllers, that are embedded in the processor or delivered as standalone components, are designed alongside the processor to match the processor requirements and easily integrate into AMBA AXI or AHB interconnects. 

The CoreLink L2C-310 cache controller is a high-performance, AXI level 2 cache controller that is designed and optimized to address Arm AXI processors, such as the Cortex-A9, Cortex-A5, Cortex-R4, Cortex-R5, Cortex-R7, Arm11MPCore, Arm1176, and Arm1156. The Mali-200 graphics processor can also benefit from this product.

Click to view the L2C-310 TRM.

  • Manual containing technical information.
  • L2C-310 TRM

    AMBA Level 2 Cache Controller designs boost the performance of AMBA AHB and AXI processors while reducing overall traffic to system memory, and therefore reducing the energy consumption of the SoC.

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Not answered What is the "Integer divide unit with support for operand-dependent early termination"? 0 votes 28 views 0 replies Started 21 hours ago by jing Answer this
Answered Binary Semaphore upset by FIQ
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0 votes 808 views 20 replies Latest 3 days ago by 42Bastian Schick Answer this
Not answered Identifying Generic IP Components on an Access Port 0 votes 48 views 0 replies Started 3 days ago by Torsten Robitzki Answer this
Not answered Issue with WatchDog reset De-asserting 0 votes 53 views 0 replies Started 3 days ago by BAB Answer this
Not answered Getting processor and cache details
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Not answered Loading cortex M1 soft processor on Pynq Processor
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  • Cortex-M
0 votes 81 views 0 replies Started 5 days ago by Sivasankar Answer this
Not answered What is the "Integer divide unit with support for operand-dependent early termination"? Started 21 hours ago by jing 0 replies 28 views
Answered Binary Semaphore upset by FIQ Latest 3 days ago by 42Bastian Schick 20 replies 808 views
Not answered Identifying Generic IP Components on an Access Port Started 3 days ago by Torsten Robitzki 0 replies 48 views
Not answered Issue with WatchDog reset De-asserting Started 3 days ago by BAB 0 replies 53 views
Not answered Getting processor and cache details Started 5 days ago by karthikeyan.d 0 replies 102 views
Not answered Loading cortex M1 soft processor on Pynq Processor Started 5 days ago by Sivasankar 0 replies 81 views