CoreLink AHB Cache
Memory sizes required for applications are increasing for both on and off-chip memories across various technologies such as SRAM, PSRAM, Flash and DRAM. Typically, a larger size has a direct implication on the memory access latency. Slower memories and higher latency memories could have a significant impact on the system performance of AHB-based processors. As the capabilities of microcontrollers are set to increase over time, a solution is required to store frequently used data, and ensure system performance does not reduce.
The Arm CoreLink AHB Cache has been designed to reduce the impact of high system memory latency. It is a versatile cache for data and code. Depending on the application, when the AHB Cache has many cache hits, it lowers an SoCs power and overall memory access latency due to reduced system memory access.
Other key features include:
- 4-way set associative
- Zero bus wait state when the access is a cache hit.
- Cache size of 2kB to 64kB
- Cache line size of 32B
- Configurable Write-Through or write-back policy
- Pseudo-random replacement policy
- Support for hit and miss counters.
- Supports Q-Channel based power control.
- Supports software cache maintenance operations
CoreLink AHB Cache can be added to a system in several configurations for different IoT and embedded use cases. It supports 32-bit AMBA 5 AHB with TrustZone for Armv8-M support. It is compatible with the following processor IP:
View the CoreLink AHB Cache Technical Reference Manual: