Getting Started

AMBA system controllers are a collection of controller IP that Arm offers. These controllers are for Direct Memory Access (DMA), Level 2 Cache, and peripherals. These controllers are low-power, high-performance IP cores that perform critical tasks within the AMBA system. Designed for optimal compatibility with Arm Cortex, Mali multimedia, and CoreLink System IP, they are the natural complement to interconnect and memory controllers.


CoreLink L2C-310 level 2 cache controller

Processor to off-chip memory communication has become the performance bottleneck in many SoCs. Level 2 cache controllers improve processor performance by keeping memory access on-chip with a typical latency 10-25% of accessing the data off-chip. At the same time, the reduced processor demands on the off-chip memory bandwidth free up that resource for other masters. Level 2 cache controllers also contribute significantly to power efficiency because on-chip accesses are typically an order of magnitude lower in power when compared to going off-chip. CoreLink level 2 cache controllers, that are embedded in the processor or delivered as standalone components, are designed alongside the processor to match the processor requirements and easily integrate into AMBA AXI or AHB interconnects. 

The CoreLink L2C-310 cache controller is a high-performance, AXI level 2 cache controller that is designed and optimized to address Arm AXI processors, such as the Cortex-A9, Cortex-A5, Cortex-R4, Cortex-R5, Cortex-R7, Arm11MPCore, Arm1176, and Arm1156. The Mali-200 graphics processor can also benefit from this product.

Click to view the L2C-310 TRM.

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Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

  • Manual containing technical information.
  • L2C-310 TRM

    AMBA Level 2 Cache Controller designs boost the performance of AMBA AHB and AXI processors while reducing overall traffic to system memory, and therefore reducing the energy consumption of the SoC.

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Not answered Running .elf file on zynq board ubuntu platform 0 votes 48 views 0 replies Started 23 hours ago by dolly1192 Answer this
Answered hardfault error
  • Cortex-M4
0 votes 925 views 4 replies Latest 3 days ago by 42Bastian Schick Answer this
Not answered WID not present in AXI4 0 votes 126 views 0 replies Started 3 days ago by Ravi V. Answer this
Suggested answer Can I run an A9 program under A53 without any modification 0 votes 839 views 1 replies Latest 3 days ago by 42Bastian Schick Answer this
Suggested answer what can I get from cortex M0 design start pro?Whether I can get the RTL describle of Cortex M0(not obfuscated RTL) 0 votes 245 views 2 replies Latest 4 days ago by qinwenjian Answer this
Not answered Vacuum pump waste gas treatment equipment 0 votes 184 views 0 replies Started 4 days ago by lay1014 Answer this
Not answered Running .elf file on zynq board ubuntu platform Started 23 hours ago by dolly1192 0 replies 48 views
Answered hardfault error Latest 3 days ago by 42Bastian Schick 4 replies 925 views
Not answered WID not present in AXI4 Started 3 days ago by Ravi V. 0 replies 126 views
Suggested answer Can I run an A9 program under A53 without any modification Latest 3 days ago by 42Bastian Schick 1 replies 839 views
Suggested answer what can I get from cortex M0 design start pro?Whether I can get the RTL describle of Cortex M0(not obfuscated RTL) Latest 4 days ago by qinwenjian 2 replies 245 views
Not answered Vacuum pump waste gas treatment equipment Started 4 days ago by lay1014 0 replies 184 views