CoreLink L2C-310 level 2 cache controller
Processor to off-chip memory communication has become the performance bottleneck in many SoCs. Level 2 cache controllers improve processor performance by keeping memory access on-chip with a typical latency 10-25% of accessing the data off-chip. At the same time, the reduced processor demands on the off-chip memory bandwidth free up that resource for other masters. Level 2 cache controllers also contribute significantly to power efficiency because on-chip accesses are typically an order of magnitude lower in power when compared to going off-chip. CoreLink level 2 cache controllers, that are embedded in the processor or delivered as standalone components, are designed alongside the processor to match the processor requirements and easily integrate into AMBA AXI or AHB interconnects.
The CoreLink L2C-310 cache controller is a high-performance, AXI level 2 cache controller that is designed and optimized to address Arm AXI processors, such as the Cortex-A9, Cortex-A5, Cortex-R4, Cortex-R5, Cortex-R7, Arm11MPCore, Arm1176, and Arm1156. The Mali-200 graphics processor can also benefit from this product.
Click to view the L2C-310 TRM.