Getting Started

AMBA system controllers are a collection of controller IP that Arm offers. These controllers are for Direct Memory Access (DMA), Level 2 Cache, and peripherals. These controllers are low-power, high-performance IP cores that perform critical tasks within the AMBA system. Designed for optimal compatibility with Arm Cortex, Mali multimedia, and CoreLink System IP, they are the natural complement to interconnect and memory controllers.


CoreLink L2C-310 level 2 cache controller

Processor to off-chip memory communication has become the performance bottleneck in many SoCs. Level 2 cache controllers improve processor performance by keeping memory access on-chip with a typical latency 10-25% of accessing the data off-chip. At the same time, the reduced processor demands on the off-chip memory bandwidth free up that resource for other masters. Level 2 cache controllers also contribute significantly to power efficiency because on-chip accesses are typically an order of magnitude lower in power when compared to going off-chip. CoreLink level 2 cache controllers, that are embedded in the processor or delivered as standalone components, are designed alongside the processor to match the processor requirements and easily integrate into AMBA AXI or AHB interconnects. 

The CoreLink L2C-310 cache controller is a high-performance, AXI level 2 cache controller that is designed and optimized to address Arm AXI processors, such as the Cortex-A9, Cortex-A5, Cortex-R4, Cortex-R5, Cortex-R7, Arm11MPCore, Arm1176, and Arm1156. The Mali-200 graphics processor can also benefit from this product.

Click to view the L2C-310 TRM.

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  • Manual containing technical information.
  • L2C-310 TRM

    AMBA Level 2 Cache Controller designs boost the performance of AMBA AHB and AXI processors while reducing overall traffic to system memory, and therefore reducing the energy consumption of the SoC.

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Community Forums

Not answered making physical memory pages not cacheable (probabaly by modifying page table entry) 0 votes 44 views 0 replies Started 10 hours ago by Gol Answer this
Suggested answer Debug Connection Cause ExecutionTiming Problem on Second Core of Cortex A9 on Zynq 702 MPCore
  • System on Chip (SoC)
  • Cortex-A9
0 votes 1359 views 3 replies Latest 11 hours ago by BurakSeker Answer this
Not answered STM32F769i-Discovery IP Camera Interface 0 votes 64 views 0 replies Started 16 hours ago by Kiran bhat Answer this
Suggested answer Store operations where the cache line is already cached (ACE protocol)
  • AMBA
  • AMBA 4
  • AXI
  • Interface
2 votes 6172 views 9 replies Latest 18 hours ago by het Answer this
Not answered PendSV target secure state 0 votes 48 views 0 replies Started yesterday by Jiameng Answer this
Suggested answer Processor halt in __libc_init_array assembler function 0 votes 1262 views 6 replies Latest yesterday by lammers7 Answer this
Not answered making physical memory pages not cacheable (probabaly by modifying page table entry) Started 10 hours ago by Gol 0 replies 44 views
Suggested answer Debug Connection Cause ExecutionTiming Problem on Second Core of Cortex A9 on Zynq 702 MPCore Latest 11 hours ago by BurakSeker 3 replies 1359 views
Not answered STM32F769i-Discovery IP Camera Interface Started 16 hours ago by Kiran bhat 0 replies 64 views
Suggested answer Store operations where the cache line is already cached (ACE protocol) Latest 18 hours ago by het 9 replies 6172 views
Not answered PendSV target secure state Started yesterday by Jiameng 0 replies 48 views
Suggested answer Processor halt in __libc_init_array assembler function Latest yesterday by lammers7 6 replies 1262 views