CoreLink PCK-600

Arm CoreLink PCK-600 Power Control Kit

CoreLink PCK-600 Chip.

Getting Started

The Arm CoreLink PCK-600 Power Control Kit provides a suite of system IP that is pre-verified to ease system power and clock management infrastructure integration.

Key benefits include:

  • Implements Arm recommended Power Control System Architecture (PCSA).

  • Power management orchestration through standard software interface.

  • Configurable IP scalable for all types of applications.

  • TRM

  • CoreLink PCK-600 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Read here

Specifications

The CoreLink PCK-600 is a collection of standardized and pre-verified Arm IP which is implemented to the Arm Low Power System Architecture specification. CoreLink PCK-600 is developed based on the P and Q-channel Low Power Interface (LPI) standard. Low Power Interface has seen wide adoption amongst Arm partners, who have also implemented LPI for their own IP which works with Arm IP.

Component

Highlights

Power Policy Unit (PPU)
  • Highly configurable power domain controller.
  • Supports directed and autonomous control.
  • Software, component and power switch control interfaces.

Clock Controller
  • Controller for High-level Clock Gating (HCG).
  • Manages HCG for a single clock domain.
  • HCG supported by many Arm IP products.

Q-Channel distributor
  • 1:N fan-out from a controller to components.
  • Can be configured for expansion and sequencing.

P-Channel distributor
  • 1:N fan-out from controller to components.
  • Can be configured for expansion and sequencing.
  • Configurable remapping of power modes.

Q-Channel combiner
  • N:1 fan-in from controllers to a component.
  • For control of power/voltage domain bridges.
  • Bridge must ‘close’ before any side is powered-off.
  • Bridge cannot ‘open’ until both sides are powered-on.

P-to-Q convertor
  • 1:1 protocol conversion.
  • For integrating Q-Channel components into power domains with P-Channel PPU.

CoreLink PCK-600 key features

 Eases implementation of multiple power and clock domains:

  • Low power infrastructure design within the project schedule.

  • Accelerate time-to-market with pre-verified IP.

Component configurability supports the Arm IP power and clock control feature roadmap:

  • Supports latest Arm CPU power and operation modes.

  • Designed with Arm DynamIQ technology in mind.

Aligned to PCSA guidelines:

  • Enables third-party and legacy IP.

  • Standard software interface and control.

Get Support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Forums

Not answered what action will be performed by the master based on the read and write responce in axi 4?
  • AXI
  • AXI4
 0 votes 16 views 0 replies Started 7 hours ago by Hem Patel Answer this
Answered ACE protocol : Eviction and snoop request at same time
  • AMBA
  • l1
  • ACE
  • cache
 0 votes 345 views 1 replies Latest 8 days ago by Christopher Tory Answer this
Suggested answer AXI3 write data interleaving with same AWID
  • AMBA
  • AXI
 0 votes 412 views 4 replies Latest 8 days ago by mveereshm622 Answer this
Suggested answer AHB revisions from AHB3 to AHB5
  • AMBA
  • AHB
 0 votes 153 views 1 replies Latest 9 days ago by Colin Campbell Answer this
Suggested answer Burst termination with BUSY transfer on AHB
  • AMBA
  • AHB
 0 votes 131 views 1 replies Latest 9 days ago by Colin Campbell Answer this
Suggested answer Regarding retry response
  • AMBA
  • AHB
 0 votes 124 views 1 replies Latest 9 days ago by Colin Campbell Answer this
Not answered what action will be performed by the master based on the read and write responce in axi 4? Started 7 hours ago by Hem Patel 0 replies 16 views
Answered ACE protocol : Eviction and snoop request at same time Latest 8 days ago by Christopher Tory 1 replies 345 views
Suggested answer AXI3 write data interleaving with same AWID Latest 8 days ago by mveereshm622 4 replies 412 views
Suggested answer AHB revisions from AHB3 to AHB5 Latest 9 days ago by Colin Campbell 1 replies 153 views
Suggested answer Burst termination with BUSY transfer on AHB Latest 9 days ago by Colin Campbell 1 replies 131 views
Suggested answer Regarding retry response Latest 9 days ago by Colin Campbell 1 replies 124 views