CoreLink PCK-600

Arm CoreLink PCK-600 Power Control Kit

CoreLink PCK-600 Chip.

Getting Started

The Arm CoreLink PCK-600 Power Control Kit provides a suite of system IP that is pre-verified to ease system power and clock management infrastructure integration.

Key benefits include:

  • Implements Arm recommended Power Control System Architecture (PCSA).
  • Power management orchestration through standard software interface.
  • Configurable IP scalable for all types of applications.

  • TRM
  • CoreLink PCK-600 Technical Reference Manual

    For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Read here

Specifications

The CoreLink PCK-600 is a collection of standardized and pre-verified Arm IP which is implemented to the Arm Low Power System Architecture specification. CoreLink PCK-600 is developed based on the P and Q-channel Low Power Interface (LPI) standard. Low Power Interface has seen wide adoption amongst Arm partners, who have also implemented LPI for their own IP which works with Arm IP.

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

Component

Highlights

Power Policy Unit (PPU)

  • Highly configurable power domain controller.
  • Supports directed and autonomous control.
  • Software, component and power switch control interfaces.

Clock Controller

  • Controller for High-level Clock Gating (HCG).
  • Manages HCG for a single clock domain.
  • HCG supported by many Arm IP products.

Q-Channel distributor

  • 1:N fan-out from a controller to components.
  • Can be configured for expansion and sequencing.

P-Channel distributor

  • 1:N fan-out from controller to components.
  • Can be configured for expansion and sequencing.
  • Configurable remapping of power modes.

Q-Channel combiner

  • N:1 fan-in from controllers to a component.
  • For control of power/voltage domain bridges.
  • Bridge must ‘close’ before any side is powered-off.
  • Bridge cannot ‘open’ until both sides are powered-on.

P-to-Q convertor

  • 1:1 protocol conversion.
  • For integrating Q-Channel components into power domains with P-Channel PPU.

CoreLink PCK-600 key features

 Eases implementation of multiple power and clock domains:

  • Low power infrastructure design within the project schedule.
  • Accelerate time-to-market with pre-verified IP.

Component configurability supports the Arm IP power and clock control feature roadmap:

  • Supports latest Arm CPU power and operation modes.
  • Designed with Arm DynamIQ technology in mind.

Aligned to PCSA guidelines:

  • Enables third-party and legacy IP.
  • Standard software interface and control.

Get Support

Community Blogs

Community Forums

Answered Forum FAQs
  • ARM Community
0 votes 5199 views 0 replies Started 8 months ago by Annie Answer this
Answered Forum FAQs
  • ARM Community
0 votes 4555 views 0 replies Started 8 months ago by Annie Answer this
Not answered HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2) 0 votes 19 views 0 replies Started 6 hours ago by Tapas Answer this
Not answered A power electronics controls in C/C++ embedded and software pointer for PC program
  • C++
  • Simulation Models
  • Arm Assembly Language (ASM)
  • firmware
  • Hardware Modelling/Simulation
  • Arm Firmware Suite
0 votes 31 views 0 replies Started 13 hours ago by Md Mubdiul Answer this
Suggested answer How to calculate AXI interleave depth and reorder depth.
  • AXI4
0 votes 3748 views 3 replies Latest 3 days ago by Koalassy Answer this
Answered One master to two slave transfer (back to back) behavior for address A (slave1) and address B (slave2) 0 votes 215 views 1 replies Latest 4 days ago by Colin Campbell Answer this
Answered Forum FAQs Started 8 months ago by Annie 0 replies 5199 views
Answered Forum FAQs Started 8 months ago by Annie 0 replies 4555 views
Not answered HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2) Started 6 hours ago by Tapas 0 replies 19 views
Not answered A power electronics controls in C/C++ embedded and software pointer for PC program Started 13 hours ago by Md Mubdiul 0 replies 31 views
Suggested answer How to calculate AXI interleave depth and reorder depth. Latest 3 days ago by Koalassy 3 replies 3748 views
Answered One master to two slave transfer (back to back) behavior for address A (slave1) and address B (slave2) Latest 4 days ago by Colin Campbell 1 replies 215 views