Getting Started

AMBA system controllers are a collection of controller IP that Arm offers. These controllers are for Direct Memory Access (DMA), Level 2 Cache, and peripherals. These controllers are low-power, high-performance IP cores that perform critical tasks within the AMBA system. Designed for optimal compatibility with Arm Cortex, Mali multimedia, and CoreLink System IP, they are the natural complement to interconnect and memory controllers.


DMA controllers

Efficient use of DMA can significantly improve system performance in multiple dimensions. For example, using a DMA controller can offload a processor and either reduce power consumption, or boost the processor performance, or a combination of both. AMBA DMA controllers are designed to complement both high-end and energy-efficient systems. They provide a centralized DMA processing capability that is high performance and highly flexible, and at the same time, is area efficient. Key product offerings for DMA controllers are: 

  • CoreLink DMA-330: The DMA-330 is a high-performance DMA controller that can boost the performance and reduce the power consumption in AXI systems.  The DMA-330 is a highly configurable device to support a wide range of applications and architectures.  The DMA-330 is programmable to support scatter-gather, memory to memory, peripheral to memory, and memory to peripheral transfers, run-from-reset, security on channels, interrupts, and peripherals.

    Click to view the DMA-330 TRM.

  • PrimeCell Micro DMA-230: The DMA-230 is a low gate count (3-10k gates) micro-DMA engine targeting Cortex-M3 systems and other low-power and cost-sensitive applications. The device offers excellent performance at low gate count and all the code is stored in system RAM rather than in registers. Using this component enables Cortex-M1 and Cortex-M3 based systems to remain low cost through reduced gate count and enabling scaling down the frequency of the processor in the system for reducing overall power consumption.

    Click to view the DMA-230 TRM.


  • Manual containing technical information.
  • DMA controllers

    The Direct Memory Access (DMA) controller enables the movement of blocks of data from peripheral to memory, memory to peripheral, or memory to memory without burdening the processor.

    DMA-330 TRM

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Blogs

Community Forums

Not answered How to defined board.txt to STM32YYXX Series?
  • Microcontroller
0 votes 36 views 0 replies Started 2 days ago by @chu!! Answer this
Not answered SMMUv2 - Arm Corelink-MMU500 on Xilinx Zynq Ultrascale+
  • CoreLink MMU-500 System Memory Management Unit
  • Armv8-A
  • SMMUv2
0 votes 45 views 0 replies Started 4 days ago by Ciro Donnarumma Answer this
Suggested answer boundary concept
  • AMBA
  • AXI
  • AHB
0 votes 349 views 3 replies Latest 6 days ago by harrykayn Answer this
Suggested answer State Machine for AHB-Lite Protocol
  • ahb-lite
  • AHB
0 votes 220 views 3 replies Latest 8 days ago by Colin Campbell Answer this
Suggested answer Amba Adaptive Traffic Profiles question
  • AMBA
0 votes 141 views 1 replies Latest 11 days ago by Matteo Maria Andreozzi Answer this
Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?
  • AXI
0 votes 221 views 2 replies Latest 12 days ago by Zax Answer this
Not answered How to defined board.txt to STM32YYXX Series? Started 2 days ago by @chu!! 0 replies 36 views
Not answered SMMUv2 - Arm Corelink-MMU500 on Xilinx Zynq Ultrascale+ Started 4 days ago by Ciro Donnarumma 0 replies 45 views
Suggested answer boundary concept Latest 6 days ago by harrykayn 3 replies 349 views
Suggested answer State Machine for AHB-Lite Protocol Latest 8 days ago by Colin Campbell 3 replies 220 views
Suggested answer Amba Adaptive Traffic Profiles question Latest 11 days ago by Matteo Maria Andreozzi 1 replies 141 views
Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst? Latest 12 days ago by Zax 2 replies 221 views