A Generic Interrupt Controller (GIC) is an exclusive block of IP that performs critical tasks of interrupt management, prioritization and routing. GICs are primarily used for boosting processor efficiency and supporting interrupt virtualization. GICs are implemented based on Arm GIC architecture which has evolved from GICv1 to latest version GICv3/v4. Arm has several generic interrupt controllers that provide a range of interrupt management solutions for all types of Arm Cortex multiprocessor systems. These controllers span from the simplest GIC-400 for systems with small CPU cores counts to GIC-600 for high-performant and multi-chip systems. GIC-600AE adds additional safety features targeting high performant ASIL B to ASIL D systems.
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The Generic Interrupt Controller family
CoreLink GIC-600AE Generic Interrupt Controller
Software compatible with GIC-600. Additional features meet safety requirements for building high performance ASIL B to ASIL D systems.
The GIC-600AE is part of Arm's Safety Ready program, a collection of products across the Arm portfolio that have been through various and rigorous levels of functional safety systematic flows and development.
GIC-600AE adds address and white noise protection on top of ECC protection of memory data and AXI4-Stream interconnect with fault detection. With shared SRAM architecture, GIC-600AE incorporates efficient functional logic duplication. All main logic is duplicated for lock-step operation, with optionally duplicated comparators. External interface between GIC-600AE and system interconnect is protected using the AMBA extensions for interface protection.
GIC-600AE incorporates a fault tolerant, programmable fault management unit for error detection and reporting via standard error records registers (Armv8.2 RAS compliant).
Safety documentation package includes a Development Interface Report, safety manual and FMEA/FMEDA analysis for specific example configuration.
CoreLink GIC-600 Generic Interrupt Controller
Detects, manages, virtualizes and distributes interrupts for Armv8.0-A processors. Configurable up to 512 processor threads per chip, up to 16 chips and 960 shared interrupts.
CoreLink GIC-600 Generic Interrupt Controller is designed to support DynamIQ cores such as Cortex-A76 and Cortex-A55 while also fully backwards compatible with v8.0 cores.
CoreLink GIC-600 supports upto 56K Locality-specific Peripheral Interrupts (LPI) generated from message-based interrupts, such as PCIe MSI/MSI-X. CoreLink GIC-600 uses affinity level routing for addressing cores. This provides scalability and ease of interrupt migration. GIC-600 is configured as a distributed network of interrupt processing and distribution blocks routed over an AXI stream interconnect delivering maximum flexibility to suit core count and SoC layout.
CoreLink GIC-600 is an Arm implementation of the latest GICv3 architecture, for more information see Arm Generic Interrupt Controller Architecture Specification version 3.0 and 4.0.
CoreLink GIC-500 Generic Interrupt Controller
Detects, manages, virtualizes and distributes interrupts for Armv8.0-A processors. Configurable up to 128 single-threaded cores and 960 shared interrupts.
CoreLink GIC-500 Generic Interrupt Controller is designed to support v8.0 cores Cortex-A73, Cortex-A72, Cortex-A57 and Cortex-A53.
CoreLink GIC-500 supports upto 56K Locality-specific Peripheral Interrupts (LPI) generated from message-based interrupts such as PCIe MSI/MSI-X. CoreLink GIC-500 uses affinity-level routing for addressing cores. This provides scalability and ease of interrupt migration.
GIC-500 is configured as a single monolithic block with a network of discrete redistribution blocks for each core to suit size and SoC layout. CoreLink GIC-500 is an Arm implementation of the latest GICv3 architecture, for more information see Arm Generic Interrupt Controller Architecture Specification version 3.0 and 4.0.
CoreLink GIC-400 Generic Interrupt Controller
Detects, manages and virtualizes interrupts for Armv7 processors. Configurable up to 8 cores and 480 shared interrupts.
CoreLink GIC-400 Generic Interrupt Controller detects, manages, virtualizes and distributes up to 480 shared interrupts between up to 8 cores in Cortex-A15 and Cortex-A7 multiprocessors.
GIC-400 can be configured to support only the required number of cores and interrupts to reduce gate count. GIC-400 implements GICv2 architecture, Security and Virtualization Extensions, for more information see Arm Generic Interrupt Controller Architecture version 2.0.
CoreLink GIC-600AE features
- Meets automotive safety requirements for building high-performance ASIL B to ASIL D systems.
- Software compatible with GIC-600 with Arm v8.2 compliant RAS reporting interface.
- Efficient functional logic duplication, ECC and address protection for SRAM.
- AMBA extensions for interface protection.
- Fault management unit to simplify error reporting, testing and integration.
CoreLink GIC-600 features
CoreLink GIC-500 features
- Builds on top of GIC-400 features by implementing GICv3 architecture, for Armv8.0-A processors.
- Supports up to 128 cores within a maximum of 32 clusters using affinity-level routing.
- Supports Interrupt Translation Services (ITS) module for ID translation and core migration for incoming message-based interrupt.
- ITS commands and translation tables are stored in DRAM.
CoreLink GIC-400 features
- Implements GICv2 architecture for Armv7 processors.
- Types of interrupts supported are: Software-Generated Interrupt (SGI), Shared Peripheral Interrupt (SPI), Private Peripheral Interrupt (PPI).
- Interrupt management supports interrupt enable/disable, setting of security and priority levels, and migration of interrupts across CPU clusters.
- Supports virtualization of interrupts by sending physical interrupts to hypervisor for creating virtual interrupts.
The CoreLink GIC-500 is a build-time configurable interrupt controller that supports up to 128 cores. The GIC-500 only supports Arm v8.0-A cores that implement the GIC CPU interface with the Standard GIC Stream Protocol interface, such as Cortex-A72, Cortex-A57 and Cortex-A53. The GIC-500 receives message-based interrupts as writes to the AXI4 slave interface or other interrupts from physical inputs. It also supports an AXI4 slave interface for configuration. The GIC-500 supports an Interrupt Translation Service (ITS) module that enables ID translation for peripherals to be programmed directly by a virtual machine. It is fully programmable via registers for managing interrupt sources, interrupt behavior and routing of interrupts to one or more cores.
Scalability and multi-chip interrupt management with GIC-600
In addition to supporting all features of CoreLink GIC-500, CoreLink GIC-600 also enables scalability of interrupt management with a distributed design within a single chip and support for multi-chip interrupt management for up to 16 chips. Private peripheral interrupt (PPI) and Software Generated Interrupt (SGI) modules can be co-located with processor clusters in the same clock and power domains. Similarly Interrupt Translation Service (ITS) modules can be located in close proximity to peripherals driving message-based interrupts such as PCIe. Incoming interrupts from these modules are routed to a centralized distributor over a flexible bi-directional flexible AXI4-Stream interconnect that enables scaling to a very large number of processor cores with minimized latency and layout/wiring congestion.
Interrupt management between multiple chips is enabled by a direct link between distributors of each chip over a free flowing cross-chip virtual channel that could utilize PCIe or similar chip-to-chip protocol for the physical transport.
CoreLink GIC-600 Technical Reference Manual
For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.GIC-600 TRM
CoreLink GIC-500 Technical Reference Manual
For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.GIC-500 TRM
CoreLink GIC-400 Technical Reference Manual
For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.GIC-400 TRM
GICv3 builds on top of GICv2, adding support for a larger number of Arm cores and also message-based interrupts.Read here
GICv2 is the second generation GIC architecture for Armv7 cores.Read here
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|Suggested answer||AXI3 write data interleaving with same AWID||0 votes||398 views||4 replies||Latest 7 days ago by mveereshm622||Answer this|
|Suggested answer||AHB revisions from AHB3 to AHB5||0 votes||148 views||1 replies||Latest 7 days ago by Colin Campbell||Answer this|
|Suggested answer||Burst termination with BUSY transfer on AHB||0 votes||127 views||1 replies||Latest 7 days ago by Colin Campbell||Answer this|
|Suggested answer||Regarding retry response||0 votes||119 views||1 replies||Latest 7 days ago by Colin Campbell||Answer this|
|Suggested answer||APB3 Slave responding when PSEL = 0||0 votes||322 views||2 replies||Latest 12 days ago by vshankar11||Answer this|
|Answered||ACE protocol : Eviction and snoop request at same time Latest 6 days ago by Christopher Tory||1 replies 334 views|
|Suggested answer||AXI3 write data interleaving with same AWID Latest 7 days ago by mveereshm622||4 replies 398 views|
|Suggested answer||AHB revisions from AHB3 to AHB5 Latest 7 days ago by Colin Campbell||1 replies 148 views|
|Suggested answer||Burst termination with BUSY transfer on AHB Latest 7 days ago by Colin Campbell||1 replies 127 views|
|Suggested answer||Regarding retry response Latest 7 days ago by Colin Campbell||1 replies 119 views|
|Suggested answer||APB3 Slave responding when PSEL = 0 Latest 12 days ago by vshankar11||2 replies 322 views|