Generic Interrupt Controllers

CoreLink GIC-600AE Generic Interrupt Controller 

Software compatible with GIC-600. Additional features meet safety requirements for building high performance ASIL B to ASIL D systems.

The GIC-600AE is part of Arm's Safety Ready program, a collection of products across the Arm portfolio that have been through various and rigorous levels of functional safety systematic flows and development. 

GIC-600AE Generic Interrupt Controller is designed to support DynamIQ cores such as Cortex-A76AE, Cortex-A76 and Cortex-A55. Fully backwards compatible with Armv8.0 cores.

GIC-600AE adds address and white noise protection on top of ECC protection of memory data and AXI4-Stream interconnect with fault detection. With shared SRAM architecture, GIC-600AE incorporates efficient functional logic duplication. All main logic is duplicated for lock-step operation, with optionally duplicated comparators. External interface between GIC-600AE and system interconnect is protected using the AMBA extensions for interface protection.

GIC-600AE incorporates a fault tolerant, programmable fault management unit for error detection and reporting via standard error records registers (Armv8.2 RAS compliant).

Safety documentation package includes a Development Interface Report, safety manual and FMEA/FMEDA analysis for specific example configuration.

CoreLink GIC-600 Generic Interrupt Controller

Detects, manages, virtualizes and distributes interrupts for Armv8.0-A processors. Configurable up to 512 processor threads per chip, up to 16 chips and 960 shared interrupts.

CoreLink GIC-600 Generic Interrupt Controller is designed to support DynamIQ cores such as Cortex-A76 and Cortex-A55 while also fully backwards compatible with v8.0 cores.

CoreLink GIC-600 supports upto 56K Locality-specific Peripheral Interrupts (LPI) generated from message-based interrupts, such as PCIe MSI/MSI-X. CoreLink GIC-600 uses affinity level routing for addressing cores. This provides scalability and ease of interrupt migration. GIC-600 is configured as a distributed network of interrupt processing and distribution blocks routed over an AXI stream interconnect delivering maximum flexibility to suit core count and SoC layout.

CoreLink GIC-600 is an Arm implementation of the latest GICv3 architecture, for more information see Arm Generic Interrupt Controller Architecture Specification version 3.0 and 4.0. 

CoreLink GIC-500 Generic Interrupt Controller

Detects, manages, virtualizes and distributes interrupts for Armv8.0-A processors. Configurable up to 128 single-threaded cores and 960 shared interrupts.

CoreLink GIC-500 Generic Interrupt Controller is designed to support v8.0 cores Cortex-A73, Cortex-A72, Cortex-A57 and Cortex-A53.

CoreLink GIC-500 supports upto 56K Locality-specific Peripheral Interrupts (LPI) generated from message-based interrupts such as PCIe MSI/MSI-X. CoreLink GIC-500 uses affinity-level routing for addressing cores. This provides scalability and ease of interrupt migration.

GIC-500 is configured as a single monolithic block with a network of discrete redistribution blocks for each core to suit size and SoC layout. CoreLink GIC-500 is an Arm implementation of the latest GICv3 architecture, for more information see Arm Generic Interrupt Controller Architecture Specification version 3.0 and 4.0.

CoreLink GIC-400 Generic Interrupt Controller

Detects, manages and virtualizes interrupts for Armv7 processors. Configurable up to 8 cores and 480 shared interrupts.

CoreLink GIC-400 Generic Interrupt Controller detects, manages, virtualizes and distributes up to 480 shared interrupts between up to 8 cores in Cortex-A15 and Cortex-A7 multiprocessors.

GIC-400 can be configured to support only the required number of cores and interrupts to reduce gate count. GIC-400 implements GICv2 architecture, Security and Virtualization Extensions, for more information see Arm Generic Interrupt Controller Architecture version 2.0.