Getting started

Arm System IP also supports various general-purpose peripheral controllers. These products augment the standard IP solutions for customers adopting Arm in various systems. The following is a list of peripheral controllers available: 


PL011

PL011 is a synthesizable Universal Asynchronous Receiver Transmitter (UART) serial port controller. 

It is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral that is developed, tested, and licensed by Arm. The UART is an AMBA slave module that connects to the Advanced Peripheral Bus (APB). The UART includes an Infrared Data Association (IrDA) Serial InfraRed (SIR) protocol ENcoder/DECoder (ENDEC).

Click to view the PL011 TRM.


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PL022

PL022 is a synthesizable Single-wire Peripheral Interface (SPI) controller, master and slave.  The PL022 supports Motorola SPI, TI SSI, and Microwire.

The PrimeCell Synchronous Serial Port (SSP) is an Advanced Microcontroller Bus Architecture (AMBA) slave block that connects to the Advanced Peripheral Bus (APB). The PrimeCell SSP is an AMBA compliant System-on-Chip (SoC) peripheral that is developed, tested, and licensed by Arm.

Click to view the PL022 TRM.


PL061

PL061 is a synthesizable General Purpose Input-Output (GPIO) controller.  The PL061 supports 8 bits with interrupt control.

The PrimeCell GPIO is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral that is developed, tested, and licensed by Arm.

The PrimeCell GPIO is an AMBA slave module that connects to the Advanced Peripheral Bus (APB). The PrimeCell GPIO provides eight programmable inputs or outputs that you can control in two modes:

  • Software mode through an APB bus interface.
  • Hardware mode through a hardware control interface.

You can create ports of different widths (for example 16, 24, 32, and 40 bits) by multiple instantiation. An interrupt interface is provided to configure any number of pins as interrupt sources. You can generate interrupts depending on a level, or a transitional value of a pin. At system reset, PrimeCell GPIO lines default to inputs. The PrimeCell GPIO interfaces with input and output pad cells using a data input, data output, and output enable per pad.

Click to view the PL061 TRM.


PL080

PL080 is a synthesizable DMA controller supporting one AHB master interface and eight DMA channels.

The DMAC is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral that is developed, tested, and licensed by Arm Limited. The DMAC is an AMBA AHB module, and connects to the Advanced High-performance Bus (AHB).

Click to view the PL080 TRM.


PL081

PL081 is a synthesizable DMA controller supporting one AHB master interface and two DMA channels.

The SMDMAC is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral that is developed, tested, and licensed by Arm. The SMDMAC is an AMBA AHB module, and connects to the Advanced High-performance Bus (AHB).

Click to view the PL081 TRM.


PL111

PL111 is a synthesizable color LCD controller supporting an AHB master and slave interface and driving TFT and STN, single and dual panel displays.

The controller is an Advanced Microcontroller Bus Architecture (AMBA) master-slave module that connects to the Advanced High-performance Bus (AHB). It is an AMBA-compliant System-on-Chip (SoC) peripheral that is developed, tested, and licensed by Arm.

The controller is a reusable soft-IP block that has been developed with the principal aim of reducing time-to-market for Application-Specific Integrated Circuit (ASIC) development.

The controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels.

Click to view the PL111 TRM.


PL192

PL192 is an advanced vectored interrupt controller supporting up to 32 vectored interrupts with programmable priority level and masking.

The PrimeCell Vectored Interrupt Controller (VIC) is an Advanced Microcontroller Bus Architecture (AMBA) compliant, System-on-Chip (SoC) peripheral that is developed, tested, and licensed by Arm.

The PrimeCell VIC provides an interface to the interrupt system, and improves interrupt latency in two ways:

  • Moves the interrupt controller to the AMBA AHB bus.
  • Provides vectored interrupt support for all interrupt sources.
  • Provides support for the Arm v6 processor VIC port, compatible with Arm11 and Arm1026EJ processors.

Click to view the PL192 TRM.


PL320

PL320 is an Inter-processor communications module for servicing interrupts. It pre-dates the GIC architecture.

The IPCM provides up to 32 mailboxes with control logic and interrupt generation to support inter-processor communication. An AHB interface enables access from source and destination cores. The IPCM:

  • Sends interrupts to other cores.
  • Passes small amounts of data to other cores.

The mailboxes within the IPCM can be available as floating resources between cores or as dedicated resources to specific cores. A source core can have multiple mailboxes and send messages in parallel.

Click to view the PL320 TRM.

Click to view the PrimeCell Inter-Processor Communications Module (PL320) Technical Reference Manual

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Suggested answer build my own board ? 0 votes 1206 views 6 replies Latest yesterday by 42Bastian Schick Answer this
Suggested answer Debug from reset vector Latest 13 hours ago by Ranjith 4 replies 504 views
Not answered In APB, Why do we use enable signal? (Don't care about PREADY) Started 20 hours ago by INNS 0 replies 31 views
Not answered DesignStart Eval : The number of INTISR in Cortex-M3 Started 21 hours ago by tomaru 0 replies 23 views
Answered cortex m7 STR fail Latest 21 hours ago by OldFoggy 4 replies 139 views
Suggested answer How does RTOS use MPU on Cortex-M? Latest 22 hours ago by 42Bastian Schick 3 replies 315 views
Suggested answer build my own board ? Latest yesterday by 42Bastian Schick 6 replies 1206 views