Static Memory Controllers

The Arm CoreLink Static Memory Controllers

Static Memory Controller Block Diagram.

Getting Started

Static or Non-volatile memory is typically a shared resource to which many different masters and processes require access. Effective, error-free access to static memory is important for both system performance and system power.

The CoreLink Static Memory Controllers (SMC) provide efficient interfaces to a wide range of types of non-volatile memory, applying the features of AMBA AXI to schedule requests to the memory in the most optimal way. They are designed for compatibility with the Arm portfolio of Memory ControllersCoreLink Interconnect and Processor solutions emphasizing low-power and high-performance operation.


Why choose a CoreLink Static Memory Controller?

Most systems with Arm processors have off-chip static (non-volatile) memories. These contain information such as object code and data files. System performance depends on being able to read and write this data efficiently and accurately. CoreLink Static Memory Controllers are available for AMBA AXI (SMC-35X) and AMBA AHB (PL24X). These controllers are optimized for the bus protocol and have been developed to complement the CoreLink Network Interconnect, and Dynamic Memory Controllers along with Arm CPU and media processors.

Verification and Benchmarking

Understanding the performance and functionality of the memory controller in a system context is critical to the specification and development of the controller. The system level verification and benchmarking ensure the delivery of products that have been fully qualified alongside the cores and on-chip interconnect. These results then drive the specifications of both current and future memory controllers. They ensure efficient, low-risk, easy to integrate solutions that enable development to proceed smoothly - meeting performance goals and delivering time to market.

And for the future?

Arm is committed to ensuring the Arm ecosystem has the memory controller solutions in demand. Arm participates in the industry standards bodies defining new memory interfaces. Collaboration with Arm teams developing new cores and new interconnects ensures that memory interface support for new products is available when needed.

How to choose

AXI Static Memory Controllers

The SMC-35X family of products provides an interface between AXI interconnects and a range of non-volatile memories. The SMC-35X has a wide range of configurable parameters, these are described under the specifications tab. 

Product

Non-Volatile Memory Supported

Notes

SMC-351

NAND Flash

up to 4 chip selects

SMC-352

NOR Flash / SRAM

up to 4 chip selects

SMC-353

NAND Flash and NOR Flash / SRAM

up to 4 NAND and 4 NOR/SRAM

SMC-354

NOR Flash / SRAM

up to 8 chip selects in 2 groups of 4


AHB Memory Controllers

The PL24X family products provide an interface between AHB interconnects and non-volatile memory. These are hybrid controllers also providing an interface to DRAM memory systems.

Other combinations of memory can be supported by using a combination of the CoreLink Network Interconnect product with DMC-34X and SMC-35X memory controllers.


 Product NV Memory Supported  DRAM Support  AHB Ports 
 PL241 NOR/SRAM  None  1
 PL242 NAND  SDR  4
 PL243 NOR/SRAM  SDR  4
 PL244 NAND  DDR  6
 PL245 NOR/SRAM  DDR  6

Other combinations of memory can be supported by using a combination of the CoreLink Network Interconnect product with DMC-34X and SMC-35X memory controllers.

 

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Blogs

Community Forums

Suggested answer boundary concept
  • AMBA
  • AXI
  • AHB
0 votes 304 views 3 replies Latest yesterday by harrykayn Answer this
Suggested answer State Machine for AHB-Lite Protocol
  • ahb-lite
  • AHB
0 votes 177 views 3 replies Latest 3 days ago by Colin Campbell Answer this
Suggested answer Amba Adaptive Traffic Profiles question
  • AMBA
0 votes 111 views 1 replies Latest 6 days ago by Matteo Maria Andreozzi Answer this
Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?
  • AXI
0 votes 185 views 2 replies Latest 7 days ago by Zax Answer this
Suggested answer Assertion for Multiple Transfer on APB Bus
  • APB
  • AMBA
  • Bus Architecture
0 votes 127 views 2 replies Latest 7 days ago by Rakesh Venkatesan Answer this
Answered What purpose do wrapping BURST transfers serve?
  • ahb-lite
  • AHB
0 votes 150 views 1 replies Latest 8 days ago by Colin Campbell Answer this
Suggested answer boundary concept Latest yesterday by harrykayn 3 replies 304 views
Suggested answer State Machine for AHB-Lite Protocol Latest 3 days ago by Colin Campbell 3 replies 177 views
Suggested answer Amba Adaptive Traffic Profiles question Latest 6 days ago by Matteo Maria Andreozzi 1 replies 111 views
Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst? Latest 7 days ago by Zax 2 replies 185 views
Suggested answer Assertion for Multiple Transfer on APB Bus Latest 7 days ago by Rakesh Venkatesan 2 replies 127 views
Answered What purpose do wrapping BURST transfers serve? Latest 8 days ago by Colin Campbell 1 replies 150 views