System Memory Management Units

The Arm System Memory Management Units

The System Memory Management Unit family

White paper: Enterprise Virtualization with Arm CoreLink SMMU and Arm CoreLink GIC

Download

Highlights

CoreLink MMU-600AE features

  • Meets automotive safety requirements for building high-performance ASIL B to ASIL D systems.
  • Software compatible with MMU-600 with Arm v8.2 compliant RAS reporting interface.
  • Efficient functional logic duplication, ECC and address protection for SRAM.
  • AMBA extensions for interface protection.
  • Fault management unit to simplify error reporting, testing and integration.

Download TRM

 

CoreLink MMU-600 features

  • Enhances CoreLink MMU-500 feature set by incorporating SMMUv3.1 specification to support Armv8.2 CPUs.
  • Expands the number of contexts supported to millions.
  • Implements AMBA-DTI to interface TBU and TCU to improve scalability.
  • Multi-level TLB and Walk Cache improves system address translation hit rates.
  • Improved write buffer depth and parallel translations.
Diagram on enterprise for CCN502 to 512.

CoreLink MMU-500 Features

  • Builds on top of MMU-400 features by implementing SMMUv2 architecture adding support for Armv8 CPUs.
  • Supports Stage 1, Stage 2, and Stage1 followed by Stage 2 address translation for up to 128 active device contexts.
  • Implements a distributed Translation Buffer Unit (TBU) micro-architecture with direct point-to-point connections between each TBU and the centralized Translation Control Unit (TCU) for Page Table Walks (PTWs).
  • Supports up to 128 entries per TLB which is further backed by TCU cache up to 2K entries.

CoreLink MMU-401 Features

  • Supports SMMUv1 architecture for Armv7 CPUs and Arm v8 for 64KB page sizes.
  • Performs stage2 translation only for hypervisor support.
  • Implements a single TBU micro-architecture with connection to a single TCU for page table walks.

MMU-500 Block Diagram

CoreLink MMU-500 Characteristics

The CoreLink MMU-500 supports the translation formats of Armv7 and Armv8 architectures and performs Stage 1, Stage 2, or Stage 1 followed by Stage 2 translations for all page sizes except 16KB page granule for Armv8. The MMU-500 is implemented as a distributed design with one or more TBUs communicating to a single centralized TCU that performs PTWs to memory. Each TBU can be located in its own clock and power domain making it easy to co-locate the TBU with the peripheral requiring translation. Each TBU communicates to the TCU over an point-to-point stream interface and with bus masters over ACE-Lite. The TCU has an AXI4 slave interface for configuration. 


Get support

Community Forums

Answered Forum FAQs
  • ARM Community
0 votes 3148 views 0 replies Started 3 months ago by Annie Cracknell Answer this
Answered Forum FAQs
  • ARM Community
0 votes 3122 views 0 replies Started 3 months ago by Annie Cracknell Answer this
Answered Embedded Linux online course 0 votes 131 views 4 replies Latest 11 hours ago by Osama Answer this
Not answered Arm Cortex A78 Linux boot up
  • Arm Community Partner
  • ARM Community
  • Armv8.1-A
0 votes 60 views 0 replies Started 4 days ago by Neel75 Answer this
Suggested answer Is anyone interested in IoT and Blockchain? An interesting Dev-Board
  • Smart Cities
  • LTE-M
  • cryptography
  • gps
  • Trustzone Cryptocell
  • Cortex-M33
0 votes 202 views 1 replies Latest 5 days ago by nRFDev Answer this
Not answered What is a NIC-400 APB Group? 0 votes 61 views 0 replies Started 5 days ago by LloydG Answer this
Answered Forum FAQs Started 3 months ago by Annie Cracknell 0 replies 3148 views
Answered Forum FAQs Started 3 months ago by Annie Cracknell 0 replies 3122 views
Answered Embedded Linux online course Latest 11 hours ago by Osama 4 replies 131 views
Not answered Arm Cortex A78 Linux boot up Started 4 days ago by Neel75 0 replies 60 views
Suggested answer Is anyone interested in IoT and Blockchain? An interesting Dev-Board Latest 5 days ago by nRFDev 1 replies 202 views
Not answered What is a NIC-400 APB Group? Started 5 days ago by LloydG 0 replies 61 views