System Controllers

CoreLink MMU-600AE

Software compatible with MMU-600. Adds additional safety features to meet safety requirements for building high-performance ASIL B to ASIL D systems.

The CoreLink MMU-600AE is part of Arm's Safety Ready program, a collection of products across the Arm portfolio that have been through various and rigorous levels of functional safety systematic flows and development. 

MMU-600AE is compatible with the Armv8.2-A enabled Cortex-A76AE, Cortex-A76 and Cortex-A55 processors. Fully backwards compatible with Armv7.0 and Armv8.0 cores.

MMU-600AE adds address and white-noise protection on top of ECC protection of memory data and AXI4-Stream interconnect with fault detection. With shared SRAM architecture, MMU-600AE incorporates efficient functional logic duplication. All main logic is duplicated for lock-step operation, with optionally duplicated comparators. External interface between MMU-600AE and system interconnect is protected using the AMBA extensions for interface protection.

MMU-600AE incorporates a fault tolerant, programmable fault management unit for error detection and reporting via standard error records registers (Armv8.2 RAS compliant).

Safety documentation package includes a Development Interface Report, safety manual and FMEA/FMEDA analysis for specific example configuration.

CoreLink MMU-600

Highly scalable and support for millions of translation contexts.

The CoreLink MMU-600 is compatible with the Armv8.2-A enabled Cortex-A76 and Cortex-A55 processors, and is backwards compatible with Armv7 and Armv8 processors. Designs can be scaled from small to large-scale systems while maintaining a common driver framework. 

Support for PCIe Gen4 enables IO accelerators to be connected for high throughput systems. 

CoreLink MMU-600’s stage 2 protection mechanism also enables TrustZone Media Protection v2 (TZMP2) with master side filtering. This protects high value 4K premium content without the need for extensive memory carve-outs.

CoreLink MMU-500

Accelerated stage 1 and stage 2 address translation for maximum flexibility.

The CoreLink MMU-500 is compatible with the Armv8-A enabled Cortex-A72 and Cortex-A53 processors, and is backwards compatible with the Arm Cortex-A15 and Arm Cortex-A7 processors. It offers nested stage 1 and stage 2 accelerated address translation with multiple distributed translation buffers controlled from a single control unit. It is compatible with a wide range of bus master types and capabilities. offering maximum flexibility in implementing efficient SoC designs that need to support virtualized applications.

CoreLink MMU-401

Accelerated stage 2 address translation to reduce hypervisor overhead.

The CoreLink MMU-401 is compatible with the Arm Cortex-A15 and Cortex-A7 processors and offers stage 2 accelerated address translation for bus masters that already implement MMU functionality for stage 1 translation, such as the Mali-400 Graphics Processor, thereby reducing the hypervisor overhead in managing complex bus master interactions.