A system memory management unit (SMMU) is responsible for all aspects of memory management, including caching and memory virtualization. It gives a common view of memory to all SoC components. It enforces memory protection and access schematic while extending memory virtualization services that match those provided by the main application processor to ensure consistent security across the SoC. The SMMU is designed for use in a virtualized system where multiple guest operating systems are managed by a hypervisor.
The System Memory Management Unit family
Software compatible with MMU-600. Adds additional safety features to meet safety requirements for building high-performance ASIL B to ASIL D systems.
The CoreLink MMU-600AE is part of Arm's Safety Ready program, a collection of products across the Arm portfolio that have been through various and rigorous levels of functional safety systematic flows and development.
MMU-600AE adds address and white-noise protection on top of ECC protection of memory data and AXI4-Stream interconnect with fault detection. With shared SRAM architecture, MMU-600AE incorporates efficient functional logic duplication. All main logic is duplicated for lock-step operation, with optionally duplicated comparators. External interface between MMU-600AE and system interconnect is protected using the AMBA extensions for interface protection.
MMU-600AE incorporates a fault tolerant, programmable fault management unit for error detection and reporting via standard error records registers (Armv8.2 RAS compliant).
Safety documentation package includes a Development Interface Report, safety manual and FMEA/FMEDA analysis for specific example configuration.
Highly scalable and support for millions of translation contexts.
The CoreLink MMU-600 is compatible with the Armv8.2-A enabled Cortex-A76 and Cortex-A55 processors, and is backwards compatible with Armv7 and Armv8 processors. Designs can be scaled from small to large-scale systems while maintaining a common driver framework.
Support for PCIe Gen4 enables IO accelerators to be connected for high throughput systems.
CoreLink MMU-600’s stage 2 protection mechanism also enables TrustZone Media Protection v2 (TZMP2) with master side filtering. This protects high value 4K premium content without the need for extensive memory carve-outs.
Accelerated stage 1 and stage 2 address translation for maximum flexibility.
The CoreLink MMU-500 is compatible with the Armv8-A enabled Cortex-A72 and Cortex-A53 processors, and is backwards compatible with the Arm Cortex-A15 and Arm Cortex-A7 processors. It offers nested stage 1 and stage 2 accelerated address translation with multiple distributed translation buffers controlled from a single control unit. It is compatible with a wide range of bus master types and capabilities. offering maximum flexibility in implementing efficient SoC designs that need to support virtualized applications.
Accelerated stage 2 address translation to reduce hypervisor overhead.
The CoreLink MMU-401 is compatible with the Arm Cortex-A15 and Cortex-A7 processors and offers stage 2 accelerated address translation for bus masters that already implement MMU functionality for stage 1 translation, such as the Mali-400 Graphics Processor, thereby reducing the hypervisor overhead in managing complex bus master interactions.
White paper: Enterprise Virtualization with Arm CoreLink SMMU and Arm CoreLink GIC
CoreLink MMU-600AE features
- Meets automotive safety requirements for building high-performance ASIL B to ASIL D systems.
- Software compatible with MMU-600 with Arm v8.2 compliant RAS reporting interface.
- Efficient functional logic duplication, ECC and address protection for SRAM.
- AMBA extensions for interface protection.
- Fault management unit to simplify error reporting, testing and integration.
CoreLink MMU-600 features
- Enhances CoreLink MMU-500 feature set by incorporating SMMUv3.1 specification to support Armv8.2 CPUs.
- Expands the number of contexts supported to millions.
- Implements AMBA-DTI to interface TBU and TCU to improve scalability.
- Multi-level TLB and Walk Cache improves system address translation hit rates.
- Improved write buffer depth and parallel translations.
CoreLink MMU-500 Features
- Builds on top of MMU-400 features by implementing SMMUv2 architecture adding support for Armv8 CPUs.
- Supports Stage 1, Stage 2, and Stage1 followed by Stage 2 address translation for up to 128 active device contexts.
- Implements a distributed Translation Buffer Unit (TBU) micro-architecture with direct point-to-point connections between each TBU and the centralized Translation Control Unit (TCU) for Page Table Walks (PTWs).
- Supports up to 128 entries per TLB which is further backed by TCU cache up to 2K entries.
CoreLink MMU-401 Features
- Supports SMMUv1 architecture for Armv7 CPUs and Arm v8 for 64KB page sizes.
- Performs stage2 translation only for hypervisor support.
- Implements a single TBU micro-architecture with connection to a single TCU for page table walks.
CoreLink MMU-500 Characteristics
The CoreLink MMU-500 supports the translation formats of Armv7 and Armv8 architectures and performs Stage 1, Stage 2, or Stage 1 followed by Stage 2 translations for all page sizes except 16KB page granule for Armv8. The MMU-500 is implemented as a distributed design with one or more TBUs communicating to a single centralized TCU that performs PTWs to memory. Each TBU can be located in its own clock and power domain making it easy to co-locate the TBU with the peripheral requiring translation. Each TBU communicates to the TCU over an point-to-point stream interface and with bus masters over ACE-Lite. The TCU has an AXI4 slave interface for configuration.
CoreLink MMU-600 Technical Reference Manual
For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.MMU-600 TRM
CoreLink MMU-500 Technical Reference Manual
For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.MMU-500 TRM
CoreLink MMU-401 Technical Reference Manual
For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.MMU-401 TRM
SMMUv3 Architecture Spec
Builds on top of SMMUv2 specification to add support for Armv8 architecture.
Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.Arm training courses Open a support case
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|Suggested answer||Amba Adaptive Traffic Profiles question||0 votes||141 views||1 replies||Latest 11 days ago by Matteo Maria Andreozzi||Answer this|
|Answered||[AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?||0 votes||221 views||2 replies||Latest 12 days ago by Zax||Answer this|
|Not answered||How to defined board.txt to STM32YYXX Series? Started 2 days ago by @chu!!||0 replies 36 views|
|Not answered||SMMUv2 - Arm Corelink-MMU500 on Xilinx Zynq Ultrascale+ Started 4 days ago by Ciro Donnarumma||0 replies 45 views|
|Suggested answer||boundary concept Latest 6 days ago by harrykayn||3 replies 349 views|
|Suggested answer||State Machine for AHB-Lite Protocol Latest 8 days ago by Colin Campbell||3 replies 220 views|
|Suggested answer||Amba Adaptive Traffic Profiles question Latest 11 days ago by Matteo Maria Andreozzi||1 replies 141 views|
|Answered||[AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst? Latest 12 days ago by Zax||2 replies 221 views|