System Memory Management Units

The Arm System Memory Management Units

The System Memory Management Unit family

White paper: Enterprise Virtualization with Arm CoreLink SMMU and Arm CoreLink GIC

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Highlights

CoreLink MMU-600AE features

  • Meets automotive safety requirements for building high-performance ASIL B to ASIL D systems.
  • Software compatible with MMU-600 with Arm v8.2 compliant RAS reporting interface.
  • Efficient functional logic duplication, ECC and address protection for SRAM.
  • AMBA extensions for interface protection.
  • Fault management unit to simplify error reporting, testing and integration.

CoreLink MMU-600 features

  • Enhances CoreLink MMU-500 feature set by incorporating SMMUv3.1 specification to support Armv8.2 CPUs.
  • Expands the number of contexts supported to millions.
  • Implements AMBA-DTI to interface TBU and TCU to improve scalability.
  • Multi-level TLB and Walk Cache improves system address translation hit rates.
  • Improved write buffer depth and parallel translations.
Diagram on enterprise for CCN502 to 512.

CoreLink MMU-500 Features

  • Builds on top of MMU-400 features by implementing SMMUv2 architecture adding support for Armv8 CPUs.
  • Supports Stage 1, Stage 2, and Stage1 followed by Stage 2 address translation for up to 128 active device contexts.
  • Implements a distributed Translation Buffer Unit (TBU) micro-architecture with direct point-to-point connections between each TBU and the centralized Translation Control Unit (TCU) for Page Table Walks (PTWs).
  • Supports up to 128 entries per TLB which is further backed by TCU cache up to 2K entries.

CoreLink MMU-401 Features

  • Supports SMMUv1 architecture for Armv7 CPUs and Arm v8 for 64KB page sizes.
  • Performs stage2 translation only for hypervisor support.
  • Implements a single TBU micro-architecture with connection to a single TCU for page table walks.

MMU-500 Block Diagram

CoreLink MMU-500 Characteristics

The CoreLink MMU-500 supports the translation formats of Armv7 and Armv8 architectures and performs Stage 1, Stage 2, or Stage 1 followed by Stage 2 translations for all page sizes except 16KB page granule for Armv8. The MMU-500 is implemented as a distributed design with one or more TBUs communicating to a single centralized TCU that performs PTWs to memory. Each TBU can be located in its own clock and power domain making it easy to co-locate the TBU with the peripheral requiring translation. Each TBU communicates to the TCU over an point-to-point stream interface and with bus masters over ACE-Lite. The TCU has an AXI4 slave interface for configuration. 


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Suggested answer strobe 0 votes 5326 views 3 replies Latest 14 hours ago by Christopher Tory Answer this
Not answered BUSY transfer just before the last transfer in a burst by a AHB Master. 0 votes 214 views 0 replies Started 21 hours ago by ISHWAR GANIGER Answer this
Suggested answer PADDR
  • APB
  • vhdl
  • AMBA 3 APB Interface
0 votes 527 views 1 replies Latest 2 days ago by Colin Campbell Answer this
Not answered ABP wrapper/ resizer 32-128 bit FPGA SoC
  • APB
  • vhdl
  • 128-bit
  • SoC FPGA
0 votes 471 views 0 replies Started 6 days ago by Rann Answer this
Answered AXI4-Relationships between the channels 0 votes 782 views 1 replies Latest 9 days ago by Colin Campbell Answer this
Suggested answer Semihosting 3.0 0 votes 1025 views 2 replies Latest 9 days ago by koendv Answer this
Suggested answer strobe Latest 14 hours ago by Christopher Tory 3 replies 5326 views
Not answered BUSY transfer just before the last transfer in a burst by a AHB Master. Started 21 hours ago by ISHWAR GANIGER 0 replies 214 views
Suggested answer PADDR Latest 2 days ago by Colin Campbell 1 replies 527 views
Not answered ABP wrapper/ resizer 32-128 bit FPGA SoC Started 6 days ago by Rann 0 replies 471 views
Answered AXI4-Relationships between the channels Latest 9 days ago by Colin Campbell 1 replies 782 views
Suggested answer Semihosting 3.0 Latest 9 days ago by koendv 2 replies 1025 views