Getting Started

TrustZone system IP blocks support the Arm TrustZone system-wide approach to security for preventing access by malicious software to memory regions and peripherals such as keyboards and screens. There are three products in this category.


TrustZone Controllers

TZC-400

CoreLink TZC-400 TrustZone Address Space Controller extends on-chip security to protect multiple regions of external memory from software attacks. It is compatible with CCI-400, NIC-400, and DMC-400 product families.

Click to view the TZC-400 TRM

BP147

PrimeCell BP147 TrustZone Protection Controller enables the Secure and Non-secure worlds to safely share peripherals. It supports an APB interface that is common to most I/O peripherals.

Click to view the BP147 TRM

BP141

PrimeCell BP141 TrustZone Internal Memory Wrapper manages a single Secure region with on-chip SRAM memory

Click to view the BP141 TRM

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

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Arm support

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Community Blogs

Community Forums

Answered 32-bit encoding hex values for Arm instructions 0 votes 298 views 3 replies Latest yesterday by BQL Answer this
Answered Cycle count for a subroutine on Cortex M33 0 votes 289 views 2 replies Latest 4 days ago by Ed Player Answer this
Answered Where to find hard core Arm books, courses, tutorials
  • Arm7tdmi
0 votes 2261 views 6 replies Latest 5 days ago by drake00 Answer this
Answered Debug Unit Cortex - R 0 votes 384 views 3 replies Latest 7 days ago by Martin Weidmann Answer this
Answered Disable data prefetching in a Cortex-A53 running Android
  • Cortex-A53
  • EL1
  • L1
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0 votes 992 views 6 replies Latest 11 days ago by DNovo Answer this
Answered How to determine which core is generating the AXI read transaction in a multi core processor?
  • Cortex-A72
0 votes 762 views 3 replies Latest 11 days ago by MNB Answer this
Answered 32-bit encoding hex values for Arm instructions Latest yesterday by BQL 3 replies 298 views
Answered Cycle count for a subroutine on Cortex M33 Latest 4 days ago by Ed Player 2 replies 289 views
Answered Where to find hard core Arm books, courses, tutorials Latest 5 days ago by drake00 6 replies 2261 views
Answered Debug Unit Cortex - R Latest 7 days ago by Martin Weidmann 3 replies 384 views
Answered Disable data prefetching in a Cortex-A53 running Android Latest 11 days ago by DNovo 6 replies 992 views
Answered How to determine which core is generating the AXI read transaction in a multi core processor? Latest 11 days ago by MNB 3 replies 762 views