Getting Started

TrustZone system IP blocks support the Arm TrustZone system-wide approach to security for preventing access by malicious software to memory regions and peripherals such as keyboards and screens. There are three products in this category.


TrustZone Controllers

TZC-400

CoreLink TZC-400 TrustZone Address Space Controller extends on-chip security to protect multiple regions of external memory from software attacks. It is compatible with CCI-400, NIC-400, and DMC-400 product families.

Click to view the TZC-400 TRM

BP147

PrimeCell BP147 TrustZone Protection Controller enables the Secure and Non-secure worlds to safely share peripherals. It supports an APB interface that is common to most I/O peripherals.

Click to view the BP147 TRM

BP141

PrimeCell BP141 TrustZone Internal Memory Wrapper manages a single Secure region with on-chip SRAM memory

Click to view the BP141 TRM

Start designing now

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you’re ready to manufacture.

Get support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Open a support case

Community Forums

Answered Address memory of the next instruction in A9 MPCore
  • R15 (PC Program Counter)
0 votes 1427 views 3 replies Latest 7 days ago by dVaquerizo Answer this
Answered How to flush write buffer when memory attribute is normal_nc
  • Cache coherency
0 votes 1625 views 4 replies Latest 7 days ago by bamvor_china Answer this
Answered Is a MOV using high registers (R8-R15) possible with the ARMv6-M architecture?
  • Armv6-M
  • Documentation
0 votes 606 views 3 replies Latest 9 days ago by 42Bastian Schick Answer this
Answered How to specify virtual Address for pl011 uart in linux kernel
  • APB Peripherals
  • Arm11
  • PrimeCell UART (PL011)
  • Interrupt
0 votes 8279 views 10 replies Latest 17 days ago by Brayden Answer this
Answered how to return from exception generated by SMC instruction
  • Cortex-A53
  • EL1
  • EL3
  • EL2
  • AArch64
  • Armv8-A
  • Cortex-A
0 votes 4977 views 4 replies Latest 21 days ago by T6yson Answer this
Answered Debugging a Cortex-M0 Hard Fault
  • Armv6
  • Cortex-M0
  • Armv6-M
  • Armv7-M
  • Cortex-M3
  • Cortex-M
  • Debugging
0 votes 37160 views 6 replies Latest 21 days ago by delinaty Answer this
Answered Address memory of the next instruction in A9 MPCore Latest 7 days ago by dVaquerizo 3 replies 1427 views
Answered How to flush write buffer when memory attribute is normal_nc Latest 7 days ago by bamvor_china 4 replies 1625 views
Answered Is a MOV using high registers (R8-R15) possible with the ARMv6-M architecture? Latest 9 days ago by 42Bastian Schick 3 replies 606 views
Answered How to specify virtual Address for pl011 uart in linux kernel Latest 17 days ago by Brayden 10 replies 8279 views
Answered how to return from exception generated by SMC instruction Latest 21 days ago by T6yson 4 replies 4977 views
Answered Debugging a Cortex-M0 Hard Fault Latest 21 days ago by delinaty 6 replies 37160 views