System IP for enterprise

Getting Started

Infrastructure level systems demand sustainable on-chip bandwidth measured in terabits per second, coupled with ECC and RAS features to maintain system integrity, whilst at the same time supporting high-bandwidth IOs such as encryption engines, PCIe, SATA and multi-gigabit ethernet. To ensure the effectiveness of infrastructure class Arm Cortex processors, the whole system needs to be optimized. The CoreLink CCN Cache Coherent Network product family is specifically designed for such system optimization, enabling high bandwidth Networking and Server applications featuring 4,8 or 12 CPU cluster coherency with configurable level 3 caches.

The CCN interconnect couples tightly with the CoreLink Enterprise DMC supporting DDR4 DRAMs at the same time as managing ECC and providing RAS functionality. CoreLink NIC Non-Coherent Network Interconnect provides low latency peripheral connection, whilst CoreLink Enterprise GIC manages and distributes interrupts across multiple clusters, and even manages MSI(-X) based interrupts from sources such as PCIe. CoreLink SMMU provides IO virtualisation functions by accelerating address translation in hardware. Powerful CoreSight Debug and Trace components complete the offering and are also available for software debug and system optimization.

The net result is a secure, reliable system with non-blocking, free flowing data.


System IP Description

CoreLink Interconnect

Providing AMBA on-chip connectivity for the efficient movement of data within the system.

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CoreSight Debug Trace

A combination of IP blocks, system and software instrumentation to minimize risk and optimize performance of SoCs, from embedded to complex multi-core.

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Memory Controllers

High bandwidth and low latency access to memory across DDR3/4 memory types for best-in-class performance and power efficiency.

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System controllers

High performance IP blocks that perform critical functions within the SoC.

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IP Tooling

Software tools that automate the process of IP standardization around IP-XACT, using configuration and integration to help designers build better SoCs.

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TrustZone CryptoCell

Multi-layered hardware and software architecture combines hardware accelerators, hardware root-of-trust control with a rich layer of security software and off chip tools.

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Enterprise System Example

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Community Forums

Answered Does anyone use CMSIS-Driver specification?
  • C++
  • CMSIS
0 votes 3439 views 3 replies Latest 14 days ago by Pavel A Answer this
Answered Is AHB Slave need sample HREADY on data phase?
  • AHB-Lite
0 votes 4309 views 8 replies Latest 1 months ago by Lumi Yang Answer this
Answered why the inter-core SGI interrupt cannot be trigged on GICv3 hardware
  • Generic Interrupt Controller (GIC)
0 votes 28048 views 10 replies Latest 1 months ago by ivan_m@rocketmail.com Answer this
Answered What is the difference between "time_closure" and "present" options in NIC-400?
  • socrates
  • CoreLink NIC-400
  • CoreLink NIC-400 Network Interconnect
0 votes 2615 views 1 replies Latest 1 months ago by LloydG Answer this
Answered HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2) 0 votes 4316 views 2 replies Latest 2 months ago by Tapas Answer this
Answered One master to two slave transfer (back to back) behavior for address A (slave1) and address B (slave2) 0 votes 3965 views 2 replies Latest 2 months ago by Tapas Answer this
Answered Does anyone use CMSIS-Driver specification? Latest 14 days ago by Pavel A 3 replies 3439 views
Answered Is AHB Slave need sample HREADY on data phase? Latest 1 months ago by Lumi Yang 8 replies 4309 views
Answered why the inter-core SGI interrupt cannot be trigged on GICv3 hardware Latest 1 months ago by ivan_m@rocketmail.com 10 replies 28048 views
Answered What is the difference between "time_closure" and "present" options in NIC-400? Latest 1 months ago by LloydG 1 replies 2615 views
Answered HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2) Latest 2 months ago by Tapas 2 replies 4316 views
Answered One master to two slave transfer (back to back) behavior for address A (slave1) and address B (slave2) Latest 2 months ago by Tapas 2 replies 3965 views