System IP for enterprise

Getting Started

Infrastructure level systems demand sustainable on-chip bandwidth measured in terabits per second, coupled with ECC and RAS features to maintain system integrity, whilst at the same time supporting high-bandwidth IOs such as encryption engines, PCIe, SATA and multi-gigabit ethernet. To ensure the effectiveness of infrastructure class Arm Cortex processors, the whole system needs to be optimized. The CoreLink CCN Cache Coherent Network product family is specifically designed for such system optimization, enabling high bandwidth Networking and Server applications featuring 4,8 or 12 CPU cluster coherency with configurable level 3 caches.

The CCN interconnect couples tightly with the CoreLink Enterprise DMC supporting DDR4 DRAMs at the same time as managing ECC and providing RAS functionality. CoreLink NIC Non-Coherent Network Interconnect provides low latency peripheral connection, whilst CoreLink Enterprise GIC manages and distributes interrupts across multiple clusters, and even manages MSI(-X) based interrupts from sources such as PCIe. CoreLink SMMU provides IO virtualisation functions by accelerating address translation in hardware. Powerful CoreSight Debug and Trace components complete the offering and are also available for software debug and system optimization.

The net result is a secure, reliable system with non-blocking, free flowing data.

CoreLink Interconnect

Providing AMBA on-chip connectivity for the efficient movement of data within the system.

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CoreSight Debug Trace

A combination of IP blocks, system and software instrumentation to minimize risk and optimize performance of SoCs, from embedded to complex multi-core.

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Memory Controllers

High bandwidth and low latency access to memory across DDR3/4 memory types for best-in-class performance and power efficiency.

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System controllers

High performance IP blocks that perform critical functions within the SoC.

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IP Tooling

Software tools that automate the process of IP standardization around IP-XACT, using configuration and integration to help designers build better SoCs.

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TrustZone CryptoCell

Multi-layered hardware and software architecture combines hardware accelerators, hardware root-of-trust control with a rich layer of security software and off chip tools.

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Enterprise System Example

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Community Blogs

Community Forums

Answered Access to AHB signals 0 votes 684 views 1 replies Latest 25 days ago by Colin Campbell Answer this
Answered To generate a FIQ from ARM GIC apart from setting GICC_CTLR.FIQEn what else needs to be configured?
  • Interrupt Handling
  • System Controllers
  • Generic Interrupt Controller
  • Interrupt
0 votes 3085 views 2 replies Latest 27 days ago by Soummya Mallick Answer this
Answered why the inter-core SGI interrupt cannot be trigged on GICv3 hardware
  • Generic Interrupt Controller (GIC)
0 votes 4426 views 9 replies Latest 1 months ago by MSK Answer this
Answered how to calculate unaligned address for APB? 0 votes 851 views 6 replies Latest 1 months ago by aditya raja Answer this
Answered why PSTRB signal in APB4 have four bits?
  • APB
  • AMBA
  • AMBA 4
0 votes 1603 views 4 replies Latest 1 months ago by Colin Campbell Answer this
Answered I have a question about the destination of HWRITE data signal. 0 votes 452 views 1 replies Latest 1 months ago by Colin Campbell Answer this
Answered Access to AHB signals Latest 25 days ago by Colin Campbell 1 replies 684 views
Answered To generate a FIQ from ARM GIC apart from setting GICC_CTLR.FIQEn what else needs to be configured? Latest 27 days ago by Soummya Mallick 2 replies 3085 views
Answered why the inter-core SGI interrupt cannot be trigged on GICv3 hardware Latest 1 months ago by MSK 9 replies 4426 views
Answered how to calculate unaligned address for APB? Latest 1 months ago by aditya raja 6 replies 851 views
Answered why PSTRB signal in APB4 have four bits? Latest 1 months ago by Colin Campbell 4 replies 1603 views
Answered I have a question about the destination of HWRITE data signal. Latest 1 months ago by Colin Campbell 1 replies 452 views