System IP for enterprise

Getting Started

Infrastructure level systems demand sustainable on-chip bandwidth measured in terabits per second, coupled with ECC and RAS features to maintain system integrity, whilst at the same time supporting high-bandwidth IOs such as encryption engines, PCIe, SATA and multi-gigabit ethernet. To ensure the effectiveness of infrastructure class Arm Cortex processors, the whole system needs to be optimized. The CoreLink CCN Cache Coherent Network product family is specifically designed for such system optimization, enabling high bandwidth Networking and Server applications featuring 4,8 or 12 CPU cluster coherency with configurable level 3 caches.

The CCN interconnect couples tightly with the CoreLink Enterprise DMC supporting DDR4 DRAMs at the same time as managing ECC and providing RAS functionality. CoreLink NIC Non-Coherent Network Interconnect provides low latency peripheral connection, whilst CoreLink Enterprise GIC manages and distributes interrupts across multiple clusters, and even manages MSI(-X) based interrupts from sources such as PCIe. CoreLink SMMU provides IO virtualisation functions by accelerating address translation in hardware. Powerful CoreSight Debug and Trace components complete the offering and are also available for software debug and system optimization.

The net result is a secure, reliable system with non-blocking, free flowing data.


System IP Description

CoreLink Interconnect

Providing AMBA on-chip connectivity for the efficient movement of data within the system.

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CoreSight Debug Trace

A combination of IP blocks, system and software instrumentation to minimize risk and optimize performance of SoCs, from embedded to complex multi-core.

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Memory Controllers

High bandwidth and low latency access to memory across DDR3/4 memory types for best-in-class performance and power efficiency.

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System controllers

High performance IP blocks that perform critical functions within the SoC.

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IP Tooling

Software tools that automate the process of IP standardization around IP-XACT, using configuration and integration to help designers build better SoCs.

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TrustZone CryptoCell

Multi-layered hardware and software architecture combines hardware accelerators, hardware root-of-trust control with a rich layer of security software and off chip tools.

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Enterprise System Example

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Answered response ordering at AXI4 slave
  • AXI4
0 votes 596 views 4 replies Latest 8 days ago by rvora Answer this
Answered Can AHB3_Lite master send an unaligend address?
  • AMBA 4
  • AXI4
  • AHB-Lite
0 votes 540 views 2 replies Latest 16 days ago by Oliver Beirne Answer this
Answered AHB DeadLock: HREADY=0 & HTRANS=BUSY 0 votes 583 views 3 replies Latest 16 days ago by Oliver Beirne Answer this
Discussion IDE Recommendation
  • Cortex-M3
  • IDEs and Tool Suites
  • Cortex-M
0 votes 5497 views 6 replies Latest 21 days ago by Andy Neil Answer this
Answered AHB-lite Slave Burst Operation
  • AHB-Lite
0 votes 2312 views 4 replies Latest 25 days ago by eugch Answer this
Answered AXI transaction 0 votes 1912 views 3 replies Latest 1 months ago by Colin Campbell Answer this
Answered response ordering at AXI4 slave Latest 8 days ago by rvora 4 replies 596 views
Answered Can AHB3_Lite master send an unaligend address? Latest 16 days ago by Oliver Beirne 2 replies 540 views
Answered AHB DeadLock: HREADY=0 & HTRANS=BUSY Latest 16 days ago by Oliver Beirne 3 replies 583 views
Discussion IDE Recommendation Latest 21 days ago by Andy Neil 6 replies 5497 views
Answered AHB-lite Slave Burst Operation Latest 25 days ago by eugch 4 replies 2312 views
Answered AXI transaction Latest 1 months ago by Colin Campbell 3 replies 1912 views