System IP for enterprise

Getting Started

Infrastructure level systems demand sustainable on-chip bandwidth measured in terabits per second, coupled with ECC and RAS features to maintain system integrity, whilst at the same time supporting high-bandwidth IOs such as encryption engines, PCIe, SATA and multi-gigabit ethernet. To ensure the effectiveness of infrastructure class Arm Cortex processors, the whole system needs to be optimized. The CoreLink CCN Cache Coherent Network product family is specifically designed for such system optimization, enabling high bandwidth Networking and Server applications featuring 4,8 or 12 CPU cluster coherency with configurable level 3 caches.

The CCN interconnect couples tightly with the CoreLink Enterprise DMC supporting DDR4 DRAMs at the same time as managing ECC and providing RAS functionality. CoreLink NIC Non-Coherent Network Interconnect provides low latency peripheral connection, whilst CoreLink Enterprise GIC manages and distributes interrupts across multiple clusters, and even manages MSI(-X) based interrupts from sources such as PCIe. CoreLink SMMU provides IO virtualisation functions by accelerating address translation in hardware. Powerful CoreSight Debug and Trace components complete the offering and are also available for software debug and system optimization.

The net result is a secure, reliable system with non-blocking, free flowing data.


System IP Description

CoreLink Interconnect

Providing AMBA on-chip connectivity for the efficient movement of data within the system.

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CoreSight Debug Trace

A combination of IP blocks, system and software instrumentation to minimize risk and optimize performance of SoCs, from embedded to complex multi-core.

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Memory Controllers

High bandwidth and low latency access to memory across DDR3/4 memory types for best-in-class performance and power efficiency.

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System controllers

High performance IP blocks that perform critical functions within the SoC.

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IP Tooling

Software tools that automate the process of IP standardization around IP-XACT, using configuration and integration to help designers build better SoCs.

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TrustZone CryptoCell

Multi-layered hardware and software architecture combines hardware accelerators, hardware root-of-trust control with a rich layer of security software and off chip tools.

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Enterprise System Example

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Community Forums

Answered EMBEDDED C - Volatile qualifier does not matter in my interrupt routine
  • Cortex-M7
  • stm32 h7
0 votes 281 views 3 replies Latest 4 days ago by mingche_joe Answer this
Answered What's the purpose for WACK and RACK for ACE and what's the relationship with WVALID and RVALID ?
  • AMBA
  • ACE
0 votes 6340 views 2 replies Latest 1 months ago by George ZHAO Answer this
Answered What is the correct data in BUSY state? 0 votes 2273 views 10 replies Latest 2 months ago by Colin Campbell Answer this
Answered D-Cache read problem in EL2 mode ARM V8
  • EL2
  • ARMv8 Exception Model
0 votes 8703 views 7 replies Latest 2 months ago by gz-gz Answer this
Answered Burst termination with BUSY on AHB Lite
  • AHB-Lite
0 votes 964 views 2 replies Latest 2 months ago by Lumi Yang Answer this
Answered Embedded Linux online course 0 votes 2053 views 4 replies Latest 3 months ago by Osama Answer this
Answered EMBEDDED C - Volatile qualifier does not matter in my interrupt routine Latest 4 days ago by mingche_joe 3 replies 281 views
Answered What's the purpose for WACK and RACK for ACE and what's the relationship with WVALID and RVALID ? Latest 1 months ago by George ZHAO 2 replies 6340 views
Answered What is the correct data in BUSY state? Latest 2 months ago by Colin Campbell 10 replies 2273 views
Answered D-Cache read problem in EL2 mode ARM V8 Latest 2 months ago by gz-gz 7 replies 8703 views
Answered Burst termination with BUSY on AHB Lite Latest 2 months ago by Lumi Yang 2 replies 964 views
Answered Embedded Linux online course Latest 3 months ago by Osama 4 replies 2053 views