System IP for enterprise

Getting Started

Infrastructure level systems demand sustainable on-chip bandwidth measured in terabits per second, coupled with ECC and RAS features to maintain system integrity, whilst at the same time supporting high-bandwidth IOs such as encryption engines, PCIe, SATA and multi-gigabit ethernet. To ensure the effectiveness of infrastructure class Arm Cortex processors, the whole system needs to be optimized. The CoreLink CCN Cache Coherent Network product family is specifically designed for such system optimization, enabling high bandwidth Networking and Server applications featuring 4,8 or 12 CPU cluster coherency with configurable level 3 caches.

The CCN interconnect couples tightly with the CoreLink Enterprise DMC supporting DDR4 DRAMs at the same time as managing ECC and providing RAS functionality. CoreLink NIC Non-Coherent Network Interconnect provides low latency peripheral connection, whilst CoreLink Enterprise GIC manages and distributes interrupts across multiple clusters, and even manages MSI(-X) based interrupts from sources such as PCIe. CoreLink SMMU provides IO virtualisation functions by accelerating address translation in hardware. Powerful CoreSight Debug and Trace components complete the offering and are also available for software debug and system optimization.

The net result is a secure, reliable system with non-blocking, free flowing data.

CoreLink Interconnect

Providing AMBA on-chip connectivity for the efficient movement of data within the system.

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CoreSight Debug Trace

A combination of IP blocks, system and software instrumentation to minimize risk and optimize performance of SoCs, from embedded to complex multi-core.

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Memory Controllers

High bandwidth and low latency access to memory across DDR3/4 memory types for best-in-class performance and power efficiency.

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System controllers

High performance IP blocks that perform critical functions within the SoC.

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IP Tooling

Software tools that automate the process of IP standardization around IP-XACT, using configuration and integration to help designers build better SoCs.

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TrustZone CryptoCell

Multi-layered hardware and software architecture combines hardware accelerators, hardware root-of-trust control with a rich layer of security software and off chip tools.

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Enterprise System Example

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Community Blogs

Community Forums

Answered Regarding implementation of a scenario in AHB protocol 0 votes 176 views 4 replies Latest 3 days ago by Suyash Sharma Answer this
Answered Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior
  • AMBA
  • ACE
  • ACE 5
  • interconnect
  • AMBA 5
0 votes 2939 views 5 replies Latest 6 days ago by Christopher Tory Answer this
Answered Difference btw AXI3 and AXI4
  • AMBA
  • AXI3
  • AXI4
  • Interface
0 votes 6012 views 4 replies Latest 9 days ago by amareshpc Answer this
Answered AXI4 ordering 0 votes 1966 views 6 replies Latest 16 days ago by Hyunkyu Answer this
Answered Different STM32F405RGxx MCUs
  • STM32 F4
0 votes 888 views 4 replies Latest 17 days ago by Andy Neil Answer this
Answered AHB Bus Protocol -- Address Phase
  • Address
  • AHB-Lite
0 votes 3000 views 9 replies Latest 19 days ago by eugch Answer this
Answered Regarding implementation of a scenario in AHB protocol Latest 3 days ago by Suyash Sharma 4 replies 176 views
Answered Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior Latest 6 days ago by Christopher Tory 5 replies 2939 views
Answered Difference btw AXI3 and AXI4 Latest 9 days ago by amareshpc 4 replies 6012 views
Answered AXI4 ordering Latest 16 days ago by Hyunkyu 6 replies 1966 views
Answered Different STM32F405RGxx MCUs Latest 17 days ago by Andy Neil 4 replies 888 views
Answered AHB Bus Protocol -- Address Phase Latest 19 days ago by eugch 9 replies 3000 views