System IP for enterprise

Getting Started

Infrastructure level systems demand sustainable on-chip bandwidth measured in terabits per second, coupled with ECC and RAS features to maintain system integrity, whilst at the same time supporting high-bandwidth IOs such as encryption engines, PCIe, SATA and multi-gigabit ethernet. To ensure the effectiveness of infrastructure class Arm Cortex processors, the whole system needs to be optimized. The CoreLink CCN Cache Coherent Network product family is specifically designed for such system optimization, enabling high bandwidth Networking and Server applications featuring 4,8 or 12 CPU cluster coherency with configurable level 3 caches.

The CCN interconnect couples tightly with the CoreLink Enterprise DMC supporting DDR4 DRAMs at the same time as managing ECC and providing RAS functionality. CoreLink NIC Non-Coherent Network Interconnect provides low latency peripheral connection, whilst CoreLink Enterprise GIC manages and distributes interrupts across multiple clusters, and even manages MSI(-X) based interrupts from sources such as PCIe. CoreLink SMMU provides IO virtualisation functions by accelerating address translation in hardware. Powerful CoreSight Debug and Trace components complete the offering and are also available for software debug and system optimization.

The net result is a secure, reliable system with non-blocking, free flowing data.


System IP Description

CoreLink Interconnect

Providing AMBA on-chip connectivity for the efficient movement of data within the system.

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CoreSight Debug Trace

A combination of IP blocks, system and software instrumentation to minimize risk and optimize performance of SoCs, from embedded to complex multi-core.

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Memory Controllers

High bandwidth and low latency access to memory across DDR3/4 memory types for best-in-class performance and power efficiency.

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System controllers

High performance IP blocks that perform critical functions within the SoC.

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IP Tooling

Software tools that automate the process of IP standardization around IP-XACT, using configuration and integration to help designers build better SoCs.

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TrustZone CryptoCell

Multi-layered hardware and software architecture combines hardware accelerators, hardware root-of-trust control with a rich layer of security software and off chip tools.

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Enterprise System Example

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Community Blogs

Community Forums

Answered AXI4-Relationships between the channels 0 votes 562 views 1 replies Latest 6 days ago by Colin Campbell Answer this
Answered How to assert PSLVERR in APB4 ? 0 votes 745 views 2 replies Latest 6 days ago by PhanTam Answer this
Answered How can I learn to build my own computer with Arm processors?
  • FPGA
  • Processors
0 votes 39886 views 20 replies Latest 10 days ago by fancypants Answer this
Answered Should the SPLIT and RETRY response be given only for NONSEQ transfer? 0 votes 1106 views 4 replies Latest 11 days ago by ISHWAR GANIGER Answer this
Answered Debugging a Cortex-M0 Hard Fault
  • Armv6
  • Cortex-M0
  • Armv6-M
  • Armv7-M
  • Cortex-M3
  • Cortex-M
  • Debugging
0 votes 46658 views 7 replies Latest 11 days ago by fancypants Answer this
Answered [APB] Assert timing of PSTRB and PPROT
  • APB
  • AMBA
0 votes 1494 views 7 replies Latest 21 days ago by Taichi Ishitani Answer this
Answered AXI4-Relationships between the channels Latest 6 days ago by Colin Campbell 1 replies 562 views
Answered How to assert PSLVERR in APB4 ? Latest 6 days ago by PhanTam 2 replies 745 views
Answered How can I learn to build my own computer with Arm processors? Latest 10 days ago by fancypants 20 replies 39886 views
Answered Should the SPLIT and RETRY response be given only for NONSEQ transfer? Latest 11 days ago by ISHWAR GANIGER 4 replies 1106 views
Answered Debugging a Cortex-M0 Hard Fault Latest 11 days ago by fancypants 7 replies 46658 views
Answered [APB] Assert timing of PSTRB and PPROT Latest 21 days ago by Taichi Ishitani 7 replies 1494 views