System IP for enterprise

Getting Started

Infrastructure level systems demand sustainable on-chip bandwidth measured in terabits per second, coupled with ECC and RAS features to maintain system integrity, whilst at the same time supporting high-bandwidth IOs such as encryption engines, PCIe, SATA and multi-gigabit ethernet. To ensure the effectiveness of infrastructure class Arm Cortex processors, the whole system needs to be optimized. The CoreLink CCN Cache Coherent Network product family is specifically designed for such system optimization, enabling high bandwidth Networking and Server applications featuring 4,8 or 12 CPU cluster coherency with configurable level 3 caches.

The CCN interconnect couples tightly with the CoreLink Enterprise DMC supporting DDR4 DRAMs at the same time as managing ECC and providing RAS functionality. CoreLink NIC Non-Coherent Network Interconnect provides low latency peripheral connection, whilst CoreLink Enterprise GIC manages and distributes interrupts across multiple clusters, and even manages MSI(-X) based interrupts from sources such as PCIe. CoreLink SMMU provides IO virtualisation functions by accelerating address translation in hardware. Powerful CoreSight Debug and Trace components complete the offering and are also available for software debug and system optimization.

The net result is a secure, reliable system with non-blocking, free flowing data.


System IP Description

CoreLink Interconnect

Providing AMBA on-chip connectivity for the efficient movement of data within the system.

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CoreSight Debug Trace

A combination of IP blocks, system and software instrumentation to minimize risk and optimize performance of SoCs, from embedded to complex multi-core.

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Memory Controllers

High bandwidth and low latency access to memory across DDR3/4 memory types for best-in-class performance and power efficiency.

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System controllers

High performance IP blocks that perform critical functions within the SoC.

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IP Tooling

Software tools that automate the process of IP standardization around IP-XACT, using configuration and integration to help designers build better SoCs.

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TrustZone CryptoCell

Multi-layered hardware and software architecture combines hardware accelerators, hardware root-of-trust control with a rich layer of security software and off chip tools.

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Enterprise System Example

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Community Blogs

Community Forums

Answered ethernet sample code 0 votes 1012 views 9 replies Latest 2 days ago by SRIDHAR R Answer this
Answered Can re-order depth affect functionality of write transaction? 0 votes 722 views 5 replies Latest 12 days ago by Colin Campbell Answer this
Answered Puzzled by conflict in spec regarding memory types for AxCACHE bits 0 votes 449 views 1 replies Latest 18 days ago by Linda C. Answer this
Answered Programing Atmega328p paired with SIM900 0 votes 1516 views 8 replies Latest 20 days ago by Balvinder Answer this
Answered exporting sensor data from STM32 to a file on pc or board memory
  • STM32 L4
  • Internet of Things (IoT)
  • Sensors
0 votes 777 views 1 replies Latest 25 days ago by Andy Neil Answer this
Answered AMBA TLM 2.0 Library & AMBA-PV Extensions to TLM 0 votes 1231 views 3 replies Latest 1 months ago by Toshihisa Oishi Answer this
Answered ethernet sample code Latest 2 days ago by SRIDHAR R 9 replies 1012 views
Answered Can re-order depth affect functionality of write transaction? Latest 12 days ago by Colin Campbell 5 replies 722 views
Answered Puzzled by conflict in spec regarding memory types for AxCACHE bits Latest 18 days ago by Linda C. 1 replies 449 views
Answered Programing Atmega328p paired with SIM900 Latest 20 days ago by Balvinder 8 replies 1516 views
Answered exporting sensor data from STM32 to a file on pc or board memory Latest 25 days ago by Andy Neil 1 replies 777 views
Answered AMBA TLM 2.0 Library & AMBA-PV Extensions to TLM Latest 1 months ago by Toshihisa Oishi 3 replies 1231 views