System IP for enterprise

Getting Started

Infrastructure level systems demand sustainable on-chip bandwidth measured in terabits per second, coupled with ECC and RAS features to maintain system integrity, whilst at the same time supporting high-bandwidth IOs such as encryption engines, PCIe, SATA and multi-gigabit ethernet. To ensure the effectiveness of infrastructure class Arm Cortex processors, the whole system needs to be optimized. The CoreLink CCN Cache Coherent Network product family is specifically designed for such system optimization, enabling high bandwidth Networking and Server applications featuring 4,8 or 12 CPU cluster coherency with configurable level 3 caches.

The CCN interconnect couples tightly with the CoreLink Enterprise DMC supporting DDR4 DRAMs at the same time as managing ECC and providing RAS functionality. CoreLink NIC Non-Coherent Network Interconnect provides low latency peripheral connection, whilst CoreLink Enterprise GIC manages and distributes interrupts across multiple clusters, and even manages MSI(-X) based interrupts from sources such as PCIe. CoreLink SMMU provides IO virtualisation functions by accelerating address translation in hardware. Powerful CoreSight Debug and Trace components complete the offering and are also available for software debug and system optimization.

The net result is a secure, reliable system with non-blocking, free flowing data.


System IP Description

CoreLink Interconnect

Providing AMBA on-chip connectivity for the efficient movement of data within the system.

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CoreSight Debug Trace

A combination of IP blocks, system and software instrumentation to minimize risk and optimize performance of SoCs, from embedded to complex multi-core.

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Memory Controllers

High bandwidth and low latency access to memory across DDR3/4 memory types for best-in-class performance and power efficiency.

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System controllers

High performance IP blocks that perform critical functions within the SoC.

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IP Tooling

Software tools that automate the process of IP standardization around IP-XACT, using configuration and integration to help designers build better SoCs.

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TrustZone CryptoCell

Multi-layered hardware and software architecture combines hardware accelerators, hardware root-of-trust control with a rich layer of security software and off chip tools.

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Enterprise System Example

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Answered arm9 family nuvoton 0 votes 738 views 1 replies Latest 4 days ago by sridhar6994 Answer this
Answered NUVOTON N9H 0 votes 1520 views 6 replies Latest 4 days ago by sridhar6994 Answer this
Answered FIXED WRITE transfer of AWLEN=8'd4 in AXI4 0 votes 336 views 1 replies Latest 6 days ago by Colin Campbell Answer this
Answered Handling invalid AXI address requests
  • AXI4-Lite
  • Cortex-M System Design Kit
  • Cortex-M
0 votes 663 views 1 replies Latest 6 days ago by Colin Campbell Answer this
Answered AXI INC type transfer 0 votes 671 views 2 replies Latest 6 days ago by Ravi V. Answer this
Answered Question about AXI4 WLAST 0 votes 1076 views 1 replies Latest 12 days ago by Colin Campbell Answer this
Answered arm9 family nuvoton Latest 4 days ago by sridhar6994 1 replies 738 views
Answered NUVOTON N9H Latest 4 days ago by sridhar6994 6 replies 1520 views
Answered FIXED WRITE transfer of AWLEN=8'd4 in AXI4 Latest 6 days ago by Colin Campbell 1 replies 336 views
Answered Handling invalid AXI address requests Latest 6 days ago by Colin Campbell 1 replies 663 views
Answered AXI INC type transfer Latest 6 days ago by Ravi V. 2 replies 671 views
Answered Question about AXI4 WLAST Latest 12 days ago by Colin Campbell 1 replies 1076 views