System IP for enterprise

Getting Started

Infrastructure level systems demand sustainable on-chip bandwidth measured in terabits per second, coupled with ECC and RAS features to maintain system integrity, whilst at the same time supporting high-bandwidth IOs such as encryption engines, PCIe, SATA and multi-gigabit ethernet. To ensure the effectiveness of infrastructure class Arm Cortex processors, the whole system needs to be optimized. The CoreLink CCN Cache Coherent Network product family is specifically designed for such system optimization, enabling high bandwidth Networking and Server applications featuring 4,8 or 12 CPU cluster coherency with configurable level 3 caches.

The CCN interconnect couples tightly with the CoreLink Enterprise DMC supporting DDR4 DRAMs at the same time as managing ECC and providing RAS functionality. CoreLink NIC Non-Coherent Network Interconnect provides low latency peripheral connection, whilst CoreLink Enterprise GIC manages and distributes interrupts across multiple clusters, and even manages MSI(-X) based interrupts from sources such as PCIe. CoreLink SMMU provides IO virtualisation functions by accelerating address translation in hardware. Powerful CoreSight Debug and Trace components complete the offering and are also available for software debug and system optimization.

The net result is a secure, reliable system with non-blocking, free flowing data.


System IP Description

CoreLink Interconnect

Providing AMBA on-chip connectivity for the efficient movement of data within the system.

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CoreSight Debug Trace

A combination of IP blocks, system and software instrumentation to minimize risk and optimize performance of SoCs, from embedded to complex multi-core.

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Memory Controllers

High bandwidth and low latency access to memory across DDR3/4 memory types for best-in-class performance and power efficiency.

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System controllers

High performance IP blocks that perform critical functions within the SoC.

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IP Tooling

Software tools that automate the process of IP standardization around IP-XACT, using configuration and integration to help designers build better SoCs.

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TrustZone CryptoCell

Multi-layered hardware and software architecture combines hardware accelerators, hardware root-of-trust control with a rich layer of security software and off chip tools.

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Enterprise System Example

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Community Forums

Answered Debugging a Cortex-M0 Hard Fault
  • Armv6
  • Cortex-M0
  • Armv6-M
  • Armv7-M
  • Cortex-M3
  • Cortex-M
  • Debugging
0 votes 36977 views 6 replies Latest 18 days ago by delinaty Answer this
Answered I am working on protocol checker VC of APB4 to which I have to test the assertions written. Does it mean I have to write test cases to verify my assertions? 0 votes 1988 views 1 replies Latest 25 days ago by aditya raja Answer this
Answered Atomic access LDR/STR vs LDREX/STREX
  • AHB-Lite
  • DesignStart
0 votes 2715 views 2 replies Latest 1 months ago by EBB Answer this
Answered WSTRB calculation 0 votes 2587 views 2 replies Latest 1 months ago by Ravi V. Answer this
Answered Handshaking for the write data channel 0 votes 2885 views 3 replies Latest 1 months ago by Colin Campbell Answer this
Answered 7 inch TFT image not good for sample code 0 votes 3391 views 1 replies Latest 1 months ago by sridhar6994 Answer this
Answered Debugging a Cortex-M0 Hard Fault Latest 18 days ago by delinaty 6 replies 36977 views
Answered I am working on protocol checker VC of APB4 to which I have to test the assertions written. Does it mean I have to write test cases to verify my assertions? Latest 25 days ago by aditya raja 1 replies 1988 views
Answered Atomic access LDR/STR vs LDREX/STREX Latest 1 months ago by EBB 2 replies 2715 views
Answered WSTRB calculation Latest 1 months ago by Ravi V. 2 replies 2587 views
Answered Handshaking for the write data channel Latest 1 months ago by Colin Campbell 3 replies 2885 views
Answered 7 inch TFT image not good for sample code Latest 1 months ago by sridhar6994 1 replies 3391 views