System IP for enterprise

Getting Started

Infrastructure level systems demand sustainable on-chip bandwidth measured in terabits per second, coupled with ECC and RAS features to maintain system integrity, whilst at the same time supporting high-bandwidth IOs such as encryption engines, PCIe, SATA and multi-gigabit ethernet. To ensure the effectiveness of infrastructure class Arm Cortex processors, the whole system needs to be optimized. The CoreLink CCN Cache Coherent Network product family is specifically designed for such system optimization, enabling high bandwidth Networking and Server applications featuring 4,8 or 12 CPU cluster coherency with configurable level 3 caches.

The CCN interconnect couples tightly with the CoreLink Enterprise DMC supporting DDR4 DRAMs at the same time as managing ECC and providing RAS functionality. CoreLink NIC Non-Coherent Network Interconnect provides low latency peripheral connection, whilst CoreLink Enterprise GIC manages and distributes interrupts across multiple clusters, and even manages MSI(-X) based interrupts from sources such as PCIe. CoreLink SMMU provides IO virtualisation functions by accelerating address translation in hardware. Powerful CoreSight Debug and Trace components complete the offering and are also available for software debug and system optimization.

The net result is a secure, reliable system with non-blocking, free flowing data.

CoreLink Interconnect

Providing AMBA on-chip connectivity for the efficient movement of data within the system.

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CoreSight Debug Trace

A combination of IP blocks, system and software instrumentation to minimize risk and optimize performance of SoCs, from embedded to complex multi-core.

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Memory Controllers

High bandwidth and low latency access to memory across DDR3/4 memory types for best-in-class performance and power efficiency.

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System controllers

High performance IP blocks that perform critical functions within the SoC.

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IP Tooling

Software tools that automate the process of IP standardization around IP-XACT, using configuration and integration to help designers build better SoCs.

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TrustZone CryptoCell

Multi-layered hardware and software architecture combines hardware accelerators, hardware root-of-trust control with a rich layer of security software and off chip tools.

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Enterprise System Example

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Community Forums

Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?
  • AXI
0 votes 184 views 2 replies Latest 7 days ago by Zax Answer this
Answered What purpose do wrapping BURST transfers serve?
  • ahb-lite
  • AHB
0 votes 149 views 1 replies Latest 7 days ago by Colin Campbell Answer this
Answered Can a simple processor with load-store architecture support BURST?
  • ahb-lite
  • Processor Architecture
  • AHB
0 votes 239 views 1 replies Latest 17 days ago by Colin Campbell Answer this
Answered Why does an AHB slave require HBURST signal?
  • AHB
  • Memory
0 votes 222 views 1 replies Latest 17 days ago by Colin Campbell Answer this
Answered What purpose does BURST feature in AHB serve?
  • Protocols
  • Architecture
  • ahb-lite
  • processors
  • AHB
0 votes 211 views 1 replies Latest 17 days ago by Colin Campbell Answer this
Answered How do I add AHB interface to a processor with Load Store Architecture?
  • Processor Architecture
  • AMBA 2 AHB Interface
  • AHB
0 votes 175 views 1 replies Latest 21 days ago by Colin Campbell Answer this
Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst? Latest 7 days ago by Zax 2 replies 184 views
Answered What purpose do wrapping BURST transfers serve? Latest 7 days ago by Colin Campbell 1 replies 149 views
Answered Can a simple processor with load-store architecture support BURST? Latest 17 days ago by Colin Campbell 1 replies 239 views
Answered Why does an AHB slave require HBURST signal? Latest 17 days ago by Colin Campbell 1 replies 222 views
Answered What purpose does BURST feature in AHB serve? Latest 17 days ago by Colin Campbell 1 replies 211 views
Answered How do I add AHB interface to a processor with Load Store Architecture? Latest 21 days ago by Colin Campbell 1 replies 175 views