System IP for mobile

Getting Started

Arm System IP is designed and tested alongside Cortex processors and Mali multimedia IP and provides an optimal path from processor to DRAM, maximising throughput whilst minimising latency throughout the system. CoreLink CCI Cache Coherent Interconnects are designed to be at the heart of every big.LITTLE system providing the same view of memory to each processor, and enabling fully coherent GPU support too. CoreLink DMC Dynamic memory controllers work closely with CoreLink CCI and low latency CoreLink NIC Network Interconnects, by balancing Quality of Service interconnect requirements with efficient LPDDR3/4 DRAM scheduling, and at the same time minimising head of line blocking for maximum throughput. 

Complementing CCI, NIC and DMC are CoreLink GIC for interrupt management and distribution and CoreLink SMMU for IO virtualization by providing hardware accelerated address translation. Powerful CoreSight Debug and Trace components complete the offering and are also available for software debug and system optimization. 

The net result for the end user is fluid responsive software with the ability to support displays with 4K content whilst still remaining within a mobile power budget and footprint. 


System IP Description

CoreLink Interconnect

Providing AMBA on-chip connectivity for the efficient movement of data within the system.

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CoreSight Debug Trace

A combination of IP blocks, system and software instrumentation to minimize risk and optimize performance of SoCs, from embedded to complex multi-core.

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Memory Controllers

High bandwidth and low latency access to memory across LPDDR3/4 memory types for best-in-class performance and power efficiency.

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System Controllers

High performance IP blocks that perform critical functions within the SoC from interrupt management to address translation/IO virtualization.

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IP Tooling

Software tools that automate the process of IP standardization around IP-XACT, configuration and integration to help designers build better SoCs.

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TrustZone CryptoCell

Multi-layered hardware and software architecture combines hardware accelerators, hardware root-of-trust control with a rich layer of security software and off chip tools.

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Mobile System Example

Premium mobile system with CoreLink CCI-550

Software

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Answered HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2) 0 votes 557 views 2 replies Latest 3 days ago by Tapas Answer this
Answered One master to two slave transfer (back to back) behavior for address A (slave1) and address B (slave2) 0 votes 517 views 1 replies Latest 7 days ago by Colin Campbell Answer this
Answered Is __CC_ARM not defined in the MDK Eval Version?
  • Keil MDK
  • Keil MDK Lite Edition
0 votes 899 views 12 replies Latest 8 days ago by Grant B Answer this
Answered EMBEDDED C - Volatile qualifier does not matter in my interrupt routine
  • Cortex-M7
  • stm32 h7
0 votes 2050 views 4 replies Latest 9 days ago by Thomas M. Hamilton Answer this
Answered ARM::CMSIS 5.8.0 breaks __nop() and__disable_irq() ??
  • Keil MDK
  • STM32 F1
  • CMSIS
0 votes 730 views 3 replies Latest 17 days ago by Grant B Answer this
Answered What's the purpose for WACK and RACK for ACE and what's the relationship with WVALID and RVALID ?
  • AMBA
  • ACE
0 votes 8020 views 3 replies Latest 23 days ago by Christopher Tory Answer this
Answered HSELx behavior for One master to two slave transfer (back to back) for address A (slave1) and address B (slave2) Latest 3 days ago by Tapas 2 replies 557 views
Answered One master to two slave transfer (back to back) behavior for address A (slave1) and address B (slave2) Latest 7 days ago by Colin Campbell 1 replies 517 views
Answered Is __CC_ARM not defined in the MDK Eval Version? Latest 8 days ago by Grant B 12 replies 899 views
Answered EMBEDDED C - Volatile qualifier does not matter in my interrupt routine Latest 9 days ago by Thomas M. Hamilton 4 replies 2050 views
Answered ARM::CMSIS 5.8.0 breaks __nop() and__disable_irq() ?? Latest 17 days ago by Grant B 3 replies 730 views
Answered What's the purpose for WACK and RACK for ACE and what's the relationship with WVALID and RVALID ? Latest 23 days ago by Christopher Tory 3 replies 8020 views