System IP for mobile

Getting Started

Arm System IP is designed and tested alongside Cortex processors and Mali multimedia IP and provides an optimal path from processor to DRAM, maximising throughput whilst minimising latency throughout the system. CoreLink CCI Cache Coherent Interconnects are designed to be at the heart of every big.LITTLE system providing the same view of memory to each processor, and enabling fully coherent GPU support too. CoreLink DMC Dynamic memory controllers work closely with CoreLink CCI and low latency CoreLink NIC Network Interconnects, by balancing Quality of Service interconnect requirements with efficient LPDDR3/4 DRAM scheduling, and at the same time minimising head of line blocking for maximum throughput. 

Complementing CCI, NIC and DMC are CoreLink GIC for interrupt management and distribution and CoreLink SMMU for IO virtualization by providing hardware accelerated address translation. Powerful CoreSight Debug and Trace components complete the offering and are also available for software debug and system optimization. 

The net result for the end user is fluid responsive software with the ability to support displays with 4K content whilst still remaining within a mobile power budget and footprint. 


System IP Description

CoreLink Interconnect

Providing AMBA on-chip connectivity for the efficient movement of data within the system.

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CoreSight Debug Trace

A combination of IP blocks, system and software instrumentation to minimize risk and optimize performance of SoCs, from embedded to complex multi-core.

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Memory Controllers

High bandwidth and low latency access to memory across LPDDR3/4 memory types for best-in-class performance and power efficiency.

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System Controllers

High performance IP blocks that perform critical functions within the SoC from interrupt management to address translation/IO virtualization.

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IP Tooling

Software tools that automate the process of IP standardization around IP-XACT, configuration and integration to help designers build better SoCs.

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TrustZone CryptoCell

Multi-layered hardware and software architecture combines hardware accelerators, hardware root-of-trust control with a rich layer of security software and off chip tools.

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Mobile System Example

Premium mobile system with CoreLink CCI-550

Software

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Answered Debugging a Cortex-M0 Hard Fault
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0 votes 36790 views 6 replies Latest 15 days ago by delinaty Answer this
Answered I am working on protocol checker VC of APB4 to which I have to test the assertions written. Does it mean I have to write test cases to verify my assertions? 0 votes 1973 views 1 replies Latest 22 days ago by aditya raja Answer this
Answered Atomic access LDR/STR vs LDREX/STREX
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Answered WSTRB calculation 0 votes 2567 views 2 replies Latest 1 months ago by Ravi V. Answer this
Answered Handshaking for the write data channel 0 votes 2870 views 3 replies Latest 1 months ago by Colin Campbell Answer this
Answered 7 inch TFT image not good for sample code 0 votes 3318 views 1 replies Latest 1 months ago by sridhar6994 Answer this
Answered Debugging a Cortex-M0 Hard Fault Latest 15 days ago by delinaty 6 replies 36790 views
Answered I am working on protocol checker VC of APB4 to which I have to test the assertions written. Does it mean I have to write test cases to verify my assertions? Latest 22 days ago by aditya raja 1 replies 1973 views
Answered Atomic access LDR/STR vs LDREX/STREX Latest 1 months ago by EBB 2 replies 2695 views
Answered WSTRB calculation Latest 1 months ago by Ravi V. 2 replies 2567 views
Answered Handshaking for the write data channel Latest 1 months ago by Colin Campbell 3 replies 2870 views
Answered 7 inch TFT image not good for sample code Latest 1 months ago by sridhar6994 1 replies 3318 views