Overview

Arm System IP is designed and tested alongside Cortex processors and Mali multimedia IP and provides an optimal path from processor to DRAM, maximising throughput whilst minimising latency throughout the system. CoreLink CCI Cache Coherent Interconnects are designed to be at the heart of every big.LITTLE system providing the same view of memory to each processor, and enabling fully coherent GPU support too. CoreLink DMC Dynamic memory controllers work closely with CoreLink CCI and low latency CoreLink NIC Network Interconnects, by balancing Quality of Service interconnect requirements with efficient LPDDR3/4 DRAM scheduling, and at the same time minimising head of line blocking for maximum throughput. 

Complementing CCI, NIC and DMC are CoreLink GIC for interrupt management and distribution and CoreLink SMMU for IO virtualization by providing hardware accelerated address translation. Powerful CoreSight Debug and Trace components complete the offering and are also available for software debug and system optimization. 

The net result for the end user is fluid responsive software with the ability to support displays with 4K content whilst still remaining within a mobile power budget and footprint. 

System IP Description

CoreLink Interconnect

Providing AMBA on-chip connectivity for the efficient movement of data within the system. Learn more

CoreSight Debug & Trace

A combination of IP blocks, system and software instrumentation to minimize risk and optimize performance of SoCs, from embedded to complex multi-core. Learn more

Memory Controllers

High bandwidth and low latency access to memory across LPDDR3/4 memory types for best-in-class performance and power efficiency. Learn more

System Controllers

High performance IP blocks that perform critical functions within the SoC from interrupt management to address translation/IO virtualization. Learn more

IP Tooling

Software tools that automate the process of IP standardization around IP-XACT, configuration and integration to help designers build better SoCs. Learn more

TrustZone CryptoCell

Multi-layered hardware and software architecture combines hardware accelerators, hardware root-of-trust control with a rich layer of security software and off chip tools. Learn more

Mobile System Example

Premium mobile system with CoreLink CCI-550

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Resources

Community Forums

Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?
  • AXI
0 votes 184 views 2 replies Latest 7 days ago by Zax Answer this
Answered What purpose do wrapping BURST transfers serve?
  • ahb-lite
  • AHB
0 votes 149 views 1 replies Latest 7 days ago by Colin Campbell Answer this
Answered Can a simple processor with load-store architecture support BURST?
  • ahb-lite
  • Processor Architecture
  • AHB
0 votes 239 views 1 replies Latest 17 days ago by Colin Campbell Answer this
Answered Why does an AHB slave require HBURST signal?
  • AHB
  • Memory
0 votes 222 views 1 replies Latest 17 days ago by Colin Campbell Answer this
Answered What purpose does BURST feature in AHB serve?
  • Protocols
  • Architecture
  • ahb-lite
  • processors
  • AHB
0 votes 211 views 1 replies Latest 17 days ago by Colin Campbell Answer this
Answered How do I add AHB interface to a processor with Load Store Architecture?
  • Processor Architecture
  • AMBA 2 AHB Interface
  • AHB
0 votes 175 views 1 replies Latest 21 days ago by Colin Campbell Answer this
Answered [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst? Latest 7 days ago by Zax 2 replies 184 views
Answered What purpose do wrapping BURST transfers serve? Latest 7 days ago by Colin Campbell 1 replies 149 views
Answered Can a simple processor with load-store architecture support BURST? Latest 17 days ago by Colin Campbell 1 replies 239 views
Answered Why does an AHB slave require HBURST signal? Latest 17 days ago by Colin Campbell 1 replies 222 views
Answered What purpose does BURST feature in AHB serve? Latest 17 days ago by Colin Campbell 1 replies 211 views
Answered How do I add AHB interface to a processor with Load Store Architecture? Latest 21 days ago by Colin Campbell 1 replies 175 views