Overview

Arm System IP is designed and tested alongside Cortex processors and Mali multimedia IP and provides an optimal path from processor to DRAM, maximising throughput whilst minimising latency throughout the system. CoreLink CCI Cache Coherent Interconnects are designed to be at the heart of every big.LITTLE system providing the same view of memory to each processor, and enabling fully coherent GPU support too. CoreLink DMC Dynamic memory controllers work closely with CoreLink CCI and low latency CoreLink NIC Network Interconnects, by balancing Quality of Service interconnect requirements with efficient LPDDR3/4 DRAM scheduling, and at the same time minimising head of line blocking for maximum throughput. 

Complementing CCI, NIC and DMC are CoreLink GIC for interrupt management and distribution and CoreLink SMMU for IO virtualization by providing hardware accelerated address translation. Powerful CoreSight Debug and Trace components complete the offering and are also available for software debug and system optimization. 

The net result for the end user is fluid responsive software with the ability to support displays with 4K content whilst still remaining within a mobile power budget and footprint. 

System IP Description

CoreLink Interconnect

Providing AMBA on-chip connectivity for the efficient movement of data within the system. Learn more

CoreSight Debug & Trace

A combination of IP blocks, system and software instrumentation to minimize risk and optimize performance of SoCs, from embedded to complex multi-core. Learn more

Memory Controllers

High bandwidth and low latency access to memory across LPDDR3/4 memory types for best-in-class performance and power efficiency. Learn more

System Controllers

High performance IP blocks that perform critical functions within the SoC from interrupt management to address translation/IO virtualization. Learn more

IP Tooling

Software tools that automate the process of IP standardization around IP-XACT, configuration and integration to help designers build better SoCs. Learn more

TrustZone CryptoCell

Multi-layered hardware and software architecture combines hardware accelerators, hardware root-of-trust control with a rich layer of security software and off chip tools. Learn more

Mobile System Example

Premium mobile system with CoreLink CCI-550

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Resources

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Community Forums

Answered Regarding implementation of a scenario in AHB protocol 0 votes 85 views 4 replies Latest yesterday by Suyash Sharma Answer this
Answered Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior
  • AMBA
  • ACE
  • ACE 5
  • interconnect
  • AMBA 5
0 votes 2885 views 5 replies Latest 4 days ago by Christopher Tory Answer this
Answered Difference btw AXI3 and AXI4
  • AMBA
  • AXI3
  • AXI4
  • Interface
0 votes 5957 views 4 replies Latest 7 days ago by amareshpc Answer this
Answered AXI4 ordering 0 votes 1916 views 6 replies Latest 14 days ago by Hyunkyu Answer this
Answered Different STM32F405RGxx MCUs
  • STM32 F4
0 votes 840 views 4 replies Latest 14 days ago by Andy Neil Answer this
Answered AHB Bus Protocol -- Address Phase
  • Address
  • AHB-Lite
0 votes 2940 views 9 replies Latest 16 days ago by eugch Answer this
Answered Regarding implementation of a scenario in AHB protocol Latest yesterday by Suyash Sharma 4 replies 85 views
Answered Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior Latest 4 days ago by Christopher Tory 5 replies 2885 views
Answered Difference btw AXI3 and AXI4 Latest 7 days ago by amareshpc 4 replies 5957 views
Answered AXI4 ordering Latest 14 days ago by Hyunkyu 6 replies 1916 views
Answered Different STM32F405RGxx MCUs Latest 14 days ago by Andy Neil 4 replies 840 views
Answered AHB Bus Protocol -- Address Phase Latest 16 days ago by eugch 9 replies 2940 views