System IP for mobile

Getting Started

Arm System IP is designed and tested alongside Cortex processors and Mali multimedia IP and provides an optimal path from processor to DRAM, maximising throughput whilst minimising latency throughout the system. CoreLink CCI Cache Coherent Interconnects are designed to be at the heart of every big.LITTLE system providing the same view of memory to each processor, and enabling fully coherent GPU support too. CoreLink DMC Dynamic memory controllers work closely with CoreLink CCI and low latency CoreLink NIC Network Interconnects, by balancing Quality of Service interconnect requirements with efficient LPDDR3/4 DRAM scheduling, and at the same time minimising head of line blocking for maximum throughput. 

Complementing CCI, NIC and DMC are CoreLink GIC for interrupt management and distribution and CoreLink SMMU for IO virtualization by providing hardware accelerated address translation. Powerful CoreSight Debug and Trace components complete the offering and are also available for software debug and system optimization. 

The net result for the end user is fluid responsive software with the ability to support displays with 4K content whilst still remaining within a mobile power budget and footprint. 


System IP Description

CoreLink Interconnect

Providing AMBA on-chip connectivity for the efficient movement of data within the system.

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CoreSight Debug Trace

A combination of IP blocks, system and software instrumentation to minimize risk and optimize performance of SoCs, from embedded to complex multi-core.

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Memory Controllers

High bandwidth and low latency access to memory across LPDDR3/4 memory types for best-in-class performance and power efficiency.

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System Controllers

High performance IP blocks that perform critical functions within the SoC from interrupt management to address translation/IO virtualization.

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IP Tooling

Software tools that automate the process of IP standardization around IP-XACT, configuration and integration to help designers build better SoCs.

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TrustZone CryptoCell

Multi-layered hardware and software architecture combines hardware accelerators, hardware root-of-trust control with a rich layer of security software and off chip tools.

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Mobile System Example

Premium mobile system with CoreLink CCI-550

Software

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Answered Difference btw AXI3 and AXI4
  • AMBA
  • AXI3
  • AXI4
  • Interface
0 votes 10844 views 6 replies Latest 17 hours ago by Colin Campbell Answer this
Answered WID not present in AXI4 0 votes 236 views 1 replies Latest 17 hours ago by Colin Campbell Answer this
Answered arm9 family nuvoton 0 votes 1059 views 1 replies Latest 5 days ago by sridhar6994 Answer this
Answered NUVOTON N9H 0 votes 1853 views 6 replies Latest 6 days ago by sridhar6994 Answer this
Answered FIXED WRITE transfer of AWLEN=8'd4 in AXI4 0 votes 422 views 1 replies Latest 7 days ago by Colin Campbell Answer this
Answered Handling invalid AXI address requests
  • AXI4-Lite
  • Cortex-M System Design Kit
  • Cortex-M
0 votes 743 views 1 replies Latest 7 days ago by Colin Campbell Answer this
Answered Difference btw AXI3 and AXI4 Latest 17 hours ago by Colin Campbell 6 replies 10844 views
Answered WID not present in AXI4 Latest 17 hours ago by Colin Campbell 1 replies 236 views
Answered arm9 family nuvoton Latest 5 days ago by sridhar6994 1 replies 1059 views
Answered NUVOTON N9H Latest 6 days ago by sridhar6994 6 replies 1853 views
Answered FIXED WRITE transfer of AWLEN=8'd4 in AXI4 Latest 7 days ago by Colin Campbell 1 replies 422 views
Answered Handling invalid AXI address requests Latest 7 days ago by Colin Campbell 1 replies 743 views