System IP for mobile

Getting Started

Arm System IP is designed and tested alongside Cortex processors and Mali multimedia IP and provides an optimal path from processor to DRAM, maximising throughput whilst minimising latency throughout the system. CoreLink CCI Cache Coherent Interconnects are designed to be at the heart of every big.LITTLE system providing the same view of memory to each processor, and enabling fully coherent GPU support too. CoreLink DMC Dynamic memory controllers work closely with CoreLink CCI and low latency CoreLink NIC Network Interconnects, by balancing Quality of Service interconnect requirements with efficient LPDDR3/4 DRAM scheduling, and at the same time minimising head of line blocking for maximum throughput. 

Complementing CCI, NIC and DMC are CoreLink GIC for interrupt management and distribution and CoreLink SMMU for IO virtualization by providing hardware accelerated address translation. Powerful CoreSight Debug and Trace components complete the offering and are also available for software debug and system optimization. 

The net result for the end user is fluid responsive software with the ability to support displays with 4K content whilst still remaining within a mobile power budget and footprint. 


System IP Description

CoreLink Interconnect

Providing AMBA on-chip connectivity for the efficient movement of data within the system.

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CoreSight Debug Trace

A combination of IP blocks, system and software instrumentation to minimize risk and optimize performance of SoCs, from embedded to complex multi-core.

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Memory Controllers

High bandwidth and low latency access to memory across LPDDR3/4 memory types for best-in-class performance and power efficiency.

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System Controllers

High performance IP blocks that perform critical functions within the SoC from interrupt management to address translation/IO virtualization.

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IP Tooling

Software tools that automate the process of IP standardization around IP-XACT, configuration and integration to help designers build better SoCs.

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TrustZone CryptoCell

Multi-layered hardware and software architecture combines hardware accelerators, hardware root-of-trust control with a rich layer of security software and off chip tools.

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Mobile System Example

Premium mobile system with CoreLink CCI-550

Software

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Answered D-Cache read problem in EL2 mode ARM V8
  • EL2
  • ARMv8 Exception Model
0 votes 8011 views 7 replies Latest 18 days ago by gz-gz Answer this
Answered Burst termination with BUSY on AHB Lite
  • AHB-Lite
0 votes 507 views 2 replies Latest 21 days ago by Lumi Yang Answer this
Answered Embedded Linux online course 0 votes 1228 views 4 replies Latest 1 months ago by Osama Answer this
Answered NIC-400 Clock Relations questions in Socrates 0 votes 582 views 1 replies Latest 1 months ago by Colin Campbell Answer this
Answered New member 0 votes 1684 views 11 replies Latest 2 months ago by Andy Neil Answer this
Answered MDK Arm Keil Microvision Compiler Flash Memory Setting
  • STM32 L0
  • Cortex-M0/M0+ System Design Kit
  • MDK-Arm
  • Arm Compiler 5
0 votes 681 views 3 replies Latest 2 months ago by Oliver Beirne Answer this
Answered D-Cache read problem in EL2 mode ARM V8 Latest 18 days ago by gz-gz 7 replies 8011 views
Answered Burst termination with BUSY on AHB Lite Latest 21 days ago by Lumi Yang 2 replies 507 views
Answered Embedded Linux online course Latest 1 months ago by Osama 4 replies 1228 views
Answered NIC-400 Clock Relations questions in Socrates Latest 1 months ago by Colin Campbell 1 replies 582 views
Answered New member Latest 2 months ago by Andy Neil 11 replies 1684 views
Answered MDK Arm Keil Microvision Compiler Flash Memory Setting Latest 2 months ago by Oliver Beirne 3 replies 681 views