Cortex-M52

Key Resources

Specifications

The Arm Cortex-M52 is the smallest implementation of the Arm Helium technology, enabling enhanced DSP and ML processing with exceptionally low power consumption and area cost.

Cortex-M52 is based on the Armv8.1-M architecture and offers smallest implementation of M-profile Vector Extension (MVE). Where power and area cost are critical to the design, Cortex-M52 offers the best trade-off on performance thereby enabling partners to build the area and power-efficient MCUs and embedded SoCs for IoT and embedded applications. Use cases include MCUs for battery-operated consumer devices, wearables, and industrial control systems.

Architecture	Armv8.1-M
Bus interfaces	AMBA 5 AXI 32-bit or AMBA 5 AHB 32-bit Main system bus AMBA 5 AHB 32-bit Peripheral bus AMBA 5 AHB 32-bit TCM Access bus (subordinate port)
Pipeline	4-stage pipeline
Security	Arm TrustZone technology (optional), with optional Security Attribution Unit (SAU) of up to 8 regions. Stack limit checking. PACBTI extension (Pointer Authentication, Branch Target Identification)
Memory Protection	Optional Memory Protection Units (MPU) for process isolation with up to 16 MPU regions and a background region – if TrustZone is implemented, there can be a Secure and a Non-secure MPUs.
DSP extension	32-bit DSP/SIMD extension
Vector extension	Optional Helium technology (M-profile Vector Extension) supporting up to: 1 x 32-bit MACs/cycle 2 x 16-bit MACs/cycle 4 x 8-bit MACs/cycle
Floating-point Unit (FPU)	Optional FPU with support for half precision (fp16), single precision (fp32) and double precision (fp64) floating-point operations.
Accelerator support	Optional coprocessor interface (64-bit) supporting up to 8 coprocessor units for custom compute accelerators Optional Arm Custom Instructions
Instruction cache	Up to 64kB with ECC (optional)
Data cache	Up to 64kB with ECC (optional)
Instruction TCM (ITCM)	Up to 16MB with ECC (optional)
Data TCM (DTCM)	Up to 16MB with ECC (optional)
Interrupts	Integrated Nested Vectored Interrupt Controller (NVIC) supporting up to 480 interrupts + Non-maskable interrupt (NMI). Number of priority levels configurable from 8 to 256.
Wake-up Interrupt Controller (WIC)	Internal and/or external (optional) WIC for waking up the processor from state retention power gating or when all clocks are stopped.
Low power support	Architecturally defined Sleep and Deep Sleep modes Integrated wait for event (WFE) and wait for interrupt (WFI) instructions with Sleep On Exit functionality Sleep and Deep Sleep indication signals Multiple power domains with optional retention support for memories and logic
Debug	Hardware and software breakpoints Performance Monitoring Unit (PMU)
Trace	Optional Instruction trace with Embedded Trace Macrocell (ETM), Data Trace (DWT) (selective data trace), and Instrumentation Trace (ITM) (software trace)
Robustness	ECC on instruction cache, data cache, instruction TCM, data TCM (optional) Dual core lock step (optional) Bus interface protection (optional) PMC-100 (Programmable MBIST Controller, optional) Reliability, availability and serviceability (RAS) extension
Reference package or system example	Contact Arm

Characteristics

Performance Efficiency: 4.3 CoreMark/MHz* and 1.6 DMIPS/MHz**

Note:

* Contact Arm for compilation conditions, as well as implementation data.

** The result abides by all of the “ground rules” laid out in the Dhrystone documentation. All are with the original (K&R) v2.1 of Dhrystone. Arm Compiler 6.17.

Tools and Software

Arm Development Studio

Develop with the most comprehensive embedded C and C++ tool suite on any Arm architecture from SoC design to software development.

Keil MDK

Create, build, and debug embedded applications for Cortex-M-based microcontrollers.

Keil Studio Cloud

A browser-based IDE for IoT, ML, and embedded development. Accelerate your project with zero-installation tools, ready-to-run examples, Git integration, and web debugging.

MPS3 FPGA Prototyping Board

The Arm MPS3 FPGA prototyping board is an FPGA prototyping platform, which allows designers to design systems easily.

Common Microcontroller Software Interface Standard (CMSIS)

Simplify software reuse, and speed-up project build and debug with APIs, frameworks, and workflows for Cortex-M devices.

Trusted Firmware-M

Provides a highly configurable set of software components to create a Trusted Execution Environment (TEE) for Arm v7-M and v8-M devices.

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Support

Open a Support Case

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Design Reviews and Checklists

Our premium Design Review service helps you optimize your Arm-based System on Chip (SoC) designs, using advice from the most experienced Arm engineers in the industry. Alternatively, you can use the Design Checklists to add more confidence in your design by ensuring it meets Arm guidance and industry best practice.

Training Courses

TRAININGCortex-M System

Arm Cortex-M Efficient System Design and Development

This course is designed for engineers working on new or existing Cortex-M system designs. Configure this course according to the project requirements, including design, verification, validation, or developing software for a Cortex-M system.

TRAININGCortex-M System

TrustZone for Armv8-M Secure System Design

This course covers the architectural features that underpin the security partitioning at a software level. Learn how security can be implemented in the wider system using AMBA AHB5.

TRAININGCortex-M System

Arm Helium Technology: Digital Signal Processing with Cortex-M Processors

This course explains the benefits of Arm Helium technology, M-Profile Vector Extensions for future Cortex-M processors, and the use within Digital Signal Processing.

Works Well With

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SECURITY IP

TrustZone for Cortex-M

Arm TrustZone technology offers an efficient, system-wide approach to security with hardware-enforced isolation built into the CPU. Establish a device root of trust based on Platform Security Architecture guidelines.

CPU ARCHITECTURE

Arm Custom Instructions

Arm Custom Instructions enable bespoke data processing operations inside Arm Cortex-M processors to enhance performance, efficiency, and product differentiation..

PHYSICAL IP

Processor Implementation Kit

The Arm Processor Implementation Kit (PIK) is an implementation solution for Arm microprocessor technology that provides the fastest path to taking Arm cores to silicon.

SYSTEM IP

CoreLink DMA-350

The Arm CoreLink DMA-350 direct memory access (DMA) controller enables efficient data movement to improve system performance and power efficiency.