The Arm AMBA protocols are an open standard, on-chip interconnect specification for the connection and management of functional blocks in a System-on-Chip (SoC). It facilitates right-first-time development of multi-processor designs with large numbers of controllers and peripherals.
- AMBA5 CHI (Coherent Hub Interface) specification adds a new protocol for the interface architecture, highly scalable SoCs required by many server and networking applications.
- AMBA 5 AHB5 (Advanced High-performance Bus) is the latest addition to the AMBA family, complementing the Armv8-M architecture to extend the TrustZone security foundation from the processor to the system.
- AMBA 4 ACE - AXI Coherency Extensions - Used in big.LITTLE systems for smartphones, tablets, etc.
- AMBA 4 AXI4 - AXI4 is an update to AXI3 to enhance the performance and utilization of the interconnect when used by multiple masters.
- AMBA 3 AXI - Advanced eXtensible Interface - The most widespread AMBA interface. Connectivity up to 100's of Masters and Slaves in complex SoCs.
- AMBA 3 AHB - Advanced High-Performance Bus - The main system bus in microcontroller usage.
- AMBA 3 APB - Advanced Peripheral Bus - Minimal gate count for peripherals.
- AMBA 3 ATB - Advanced Trace Bus - For moving trace data around the chip, see CoreSight Debug and Trace.