AMBA 4 Overview

The Arm AMBA 4 specification includes AXI4 and ACE (AXI Coherency Extensions). It is targeted at high bandwidth, high clock frequency system designs and includes features that make it suitable for high-speed interconnect typical in mobile and consumer applications.

AMBA 4 Performance

The key features and benefits of the AXI protocol are:

Support for cache coherency and enforced ordering

  • AXI Coherency Extensions (ACE) enable processors to snoop each other's caches
  • ACE-Lite enables media and I/O masters to snoop and keep coherent with the processors' caches

Clock Frequency

Allows implementations to reach higher clock frequencies by making it easy to re-time without losing throughput

  • Point-to-point channel architecture


Supports Globally-Asynchronous-Locally-Synchronous (GALS) techniques for large numbers of clock domains with variable frequencies.

  • Easy addition of register stages to achieve timing closure


A split channel architecture to increase throughput by taking full advantage of deeply pipelined SDRAM memory systems.

  • Burst based transactions with only start address issued
  • Issuing of multiple outstanding addresses
  • Out of order transaction completion
  • Separate address/control and data phases

AMBA 4 Specifications

The AMBA 4 specification adds another five interface protocols on top of the AMBA 3 specifications.

The AXI and ACE protocol specification Issue E, released February 2013, adds new optional properties for AXI ordering, ACE cache behavior and Armv8 DVM messaging.



The ACE protocol, AXI Coherency Extensions, adds three additional channels for sharing data between ACE master caches and hardware control of cache maintenance. ACE also adds barrier support to enforce ordering of multiple outstanding transactions, thus minimizing CPU stalls waiting for preceding transaction to complete. Distributed Virtual Memory (DVM) signaling maintains virtual memory mapping across multiple masters.



The ACE-Lite protocol is a small subset of ACE signals that offer I/O, or one-way, coherency, where ACE masters maintain the cache coherency of ACE-Lite masters.. ACE-Lite masters can still snoop ACE master caches, but other masters cannot snoop ACE-Lite master's caches. ACE-Lite also supports barriers.



The AXI4 protocol is an update to AXI3 to enhance the performance and utilization of the interconnect when used by multiple masters. It includes the following enhancements:

  • Support for burst lengths up to 256 beats
  • Quality of Service signaling
  • Support for multiple region interfaces


The AXI4-Lite protocol is a subset of the AXI4 protocol intended for communication with simpler, smaller control register-style interfaces in components. The key features of the AXI4-Lite interface are:

  • All transactions are burst length of one
  • All data accesses are the same size as the width of the data bus
  • Exclusive accesses are not supported


The AXI4-Stream protocol is designed for unidirectional data transfers from master to slave with greatly reduced signal routing. Key features of the protocol are:

  • Supports single and multiple data streams using the same set of shared wires
  • Support for multiple data widths within the same interconnect
  • Ideal for implementation in FPGA