AMBA 5 CHI Description
The AMBA 5 CHI (Coherent Hub Interface) architecture specification defines the interfaces for connection of fully coherent processors, such as the Cortex-A75 and Cortex-A55, and dynamic memory controllers, such as the CoreLink DMC-620, to high performance, non-blocking interconnects such as the CoreLink CMN-600. It is appropriate for a wide range of applications that require coherency including mobile, networking, automotive and data center.
The CHI specification separates the protocol and transport layers to allow differing implementations to provide the optimal trade-off between performance, power and area. This separation allows interconnect designs ranging from an efficient, small cross-bar to high performance, large scale mesh network.
CHI has been architected to maintain performance as the number of components and quantity of traffic rises. This includes placing additional requirements on masters to respond to coherent snoop transactions, which means forward progress for particular masters can be more easily guaranteed in a congested system. The separation of the identification mechanism into master identifiers and transaction identifiers allows the interconnect to be constructed in a more efficient manner.
The protocol also provides a Quality of Service (QoS) mechanism to control how resources in the system shared by many processors are allocated without needing a detailed understanding of every component and how they might interact.
The AMBA 5 CHI specification is currently available to partners integrating SoCs or developing IP or tools that implement it. Please contact your Arm account manager for details on obtaining a copy.
AMBA 5 CHI Performance
The latest generation, highest performance AMBA 5 interface called CHI (Coherent Hub Interface) is targeted to provide performance with efficiency at any design point, from mobile phone to high performance computing applications. Some of the key features include:
- Support for high frequency, non-blocking coherent data transfer between many processors.
- A layered model to allow separation of communication and transport protocols for flexible topologies such as a cross-bar, ring, mesh or ad hoc.
- Cache stashing to allow accelerators or IO devices to stash critical data within a CPU cache for low latency access.
- Far atomic operations enable the interconnect to perform high frequency updates to shared data.
- End-to-end data protection and poisoning signaling.