AMBA 5 Overview

The Arm AMBA protocols are an open standard, on-chip interconnect specification for the connection and management of functional blocks in a System-on-Chip (SoC). They facilitates right-first-time development of multi-processor designs with large numbers of controllers and peripherals.

  • AMBA 5 CHI Specification

    AMBA 5 CHI (Coherent Hub Interface) specification adds a new protocol for the interface architecture, highly scalable SoCs required by many server and networking applications.

    AMBA 5 CHI
  • AMBA 5 ACE5 and AXI5 

    AMBA 5 ACE5 and AXI5 specification extends the prior generation to align with the latest AMBA 5 CHI feature set.



    ACE5 and AXI5
  • AMBA 5 AHB5 Specification

    AHB5 complements the Armv8-M architecture to extend the TrustZone security foundation from the processor to the system.


    AMBA 5 AHB5
  • AMBA 5 DTI Specification

    AMBA 5 DTI complements Arm System MMU architecture by defining a scalable message interface for translation service units.


    AMBA 5 DTI
  • AMBA Generic Flash Bus GFB

    Providing a simple interface between system and Flash.

    AMBA GFB

AMBA 5 CHI overview

The AMBA 5 CHI (Coherent Hub Interface) architecture specification defines the interfaces for connection of fully coherent processors, such as the Cortex-A75 and Cortex-A55, and dynamic memory controllers, such as the CoreLink DMC-620, to high performance, non-blocking interconnects such as the CoreLink CMN-600. It is appropriate for a wide range of applications that require coherency including mobile, networking, automotive and data center.

The CHI specification separates the protocol and transport layers to allow differing implementations to provide the optimal trade-off between performance, power and area. This separation allows interconnect designs ranging from an efficient, small cross-bar to high performance, large scale mesh network.

CHI has been architected to maintain performance as the number of components and quantity of traffic rises.  This includes placing additional requirements on masters to respond to coherent snoop transactions, which means forward progress for particular masters can be more easily guaranteed in a congested system. The separation of the identification mechanism into master identifiers and transaction identifiers allows the interconnect to be constructed in a more efficient manner.

The protocol also provides a Quality of Service (QoS) mechanism to control how resources in the system shared by many processors are allocated without needing a detailed understanding of every component and how they might interact.

The AMBA 5 CHI specification is currently available to partners integrating SoCs or developing IP or tools that implement it.  Please contact your Arm account manager for details on obtaining a copy. 

AMBA 5 CHI Performance

The latest generation, highest performance AMBA 5 interface called CHI (Coherent Hub Interface) is targeted to provide performance with efficiency at any design point, from mobile phone to high performance computing applications. Some of the key features include:

  • Support for high frequency, non-blocking coherent data transfer between many processors.
  • A layered model to allow separation of communication and transport protocols for flexible topologies such as a cross-bar, ring, mesh or ad hoc.
  • Cache stashing to allow accelerators or IO devices to stash critical data within a CPU cache for low latency access.
  • Far atomic operations enable the interconnect to perform high frequency updates to shared data.
  • End-to-end data protection and poisoning signaling.

AMBA 5 ACE5, ACE5-Lite and AXI5 overview

The AMBA AXI and ACE protocols have been used to implement high frequency, high bandwidth interconnect designs across a wide range of applications including mobile, consumer, networking, automotive, and embedded.  AMBA 5 ACE5, ACE5-Lite, and AXI5 protocols extend prior generations to include a number performance and scalability features to align and complement AMBA 5 CHI.    

Some of the new features and options include:

  • Atomic transactions.
  • Cache stashing.
  • Data protection and poisoning signaling.
  • Armv8.1 Distributed Virtual Memory (DVM) messages.
  • Quality of Service Accept signaling.
  • Persistent Cache Maintenance Operations (CMO).
  • Cache de-allocation transactions.

The new specification is available for download and includes a complete list of updates and new available features to all the ACE5 and AXI5 protocol variants. 


AMBA 5 AHB5 overview

The AMBA 5 AHB5 (Advanced High-performance Bus) architecture specification is an interface protocol most widely used with Cortex-M processors for embedded designs and other low latency SoCs.

AHB5 builds upon the previous generation AHB-Lite specification with two key goals:

  • It complements the Armv8-M architecture and extends the TrustZone security foundation from the processor to the entire system.
  • It provides consistency and alignment with AMBA AXI4 specification to:
    • Ease integration of Cortex-A and Cortex-M based systems in a SoC.
    • Allow a unified TrustZone security solution inclusive of AXI and AHB systems.

The new properties introduced in the specification are:

  • Secure/Non-secure signaling in address phase to indicate secure or non-secure transactions.
  • Extended memory types to support more complex systems.
  • Exclusive transfers that support semaphore-type operations.

AMBA 5 AHB5 provides further clarifications of AHB-Lite protocol properties as they become more widely adopted:

  • Multiple slave select for area efficiency.
  • Single-copy and multi-copy atomicity enabling scaling to multiple cores.
  • User signaling allowing for user extensions and consistency with the AMBA 4 AXI specification.

The AHB5 specification is available now for download by partners intending to build next-generation SoCs for applications including real time, IoT and embedded microcontroller designs.


AMBA 5 DTI overview

The AMBA 5 DTI (Distributed Translation Interface) protocol specification aligns with the Arm System MMU architecture to define a scalable, distributed messaging protocol for translation services. In an SMMU implementation, there are typically three components:

  • A Translation Control Unit (TCU) that performs the translation table walks.
  • A Translation Buffer Unit (TBU) that intercepts transactions in need of translation and can cache those translations to reduce transaction latency.
  • A PCI Express (PCIe) Root Complex that includes Address Translation Services (ATS). 

DTI is a point-to-point protocol where each channel consists of a link, a DTI master, and a DTI slave.  The specification outlines two different protocols between DTI masters and slaves:

  • DTI-TBU – Defines communication between a TBU master and a TCU slave.
  • DTI-ATS – Defines communication between a PCIe Root Complex and a TCU slave.

AMBA Generic Flash Bus Overview

GFB simplifies the integration of embedded Flash controllers in subsystems by providing a simple interface between the system and the Flash. GFB exists on the boundary between the master side of the Flash controller and the slave side. The master side has a generic Flash controller, which has general functions that are supported by most eFlash macros.

The slave side has the process-dependent Flash macro that is used for a specific implementation. GFB serves as the data path for accessing the flash memory resources, control related accesses are handled over other interfaces. This facilitates reusability of the general functions with different processes.