The Arm Architecture forms the basis for every Arm processor. The Arm Architecture is based upon RISC (Reduced Instruction Set Computer) principles incorporating:
- A uniform register file load/store architecture, where data processing operates only on register contents, not directly on memory contents.
- Simple addressing modes, where all load/store addresses are only determined from register contents and instruction fields.
Over time, The Arm Architecture has evolved to include architectural features to meet the growing demand for new functionality, high performance and the needs of new and emerging markets, establishing it as the leading architecture in many market segments. It supports a very broad range of performance points leading to very small implementations of Arm processors, and very efficient implementations of advanced designs using state of the art micro-architecture techniques. Key attributes of the Arm architecture are implementation size, performance, and low power consumption.
Introduction to The Arm Architecture
Enhancements to a basic RISC architecture enable Arm processors to achieve a good balance of high performance, small code size, low power consumption and small silicon area. The Arm Achitecture has evolved over time, introducing several architecture extensions throughout its history. These include:
- Security Extensions (TrustZone technology)
- Advanced SIMD (NEON technology)
- Virtualization Extensions, introduced in Armv7-A.
- Cryptographic Extensions, introduced in Armv8-A.
Arm produces a whole family of processors that share common instruction sets and programmer’s models and have some degree of backward compatibility. Processors implementing the Arm Architecture conform to a particular version of the architecture. These are:
- The Architecture (‘A’) profile for high performance markets such as mobile and enterprise.
- The Real-Time (‘R’) profile for embedded applications in automotive and industrial control.
- The Microcontroller (‘M’) profile for the microcontroller market, meeting a broad range of gate count critical, real time and performance requirements.
Latest versions (Armv8 architectures)
The latest architecture Armv8 architecture has three variants of the architecture describing processors targeting different markets:
- The Armv8-A architecture is the latest generation Arm architecture in the A-profile. It heralded the introduction of a 64-bit (AArch64) architecture alongside the well-established 32-bit (AArch32) architecture, and allows different levels of AArch64 and AArch32 support.
- The Armv8-R architecture is the latest generation Arm architecture in the R-profile. This architecture includes a deterministic memory structure and a Memory Protection Unit (MPU), and supports the A32 and T32 instruction sets.
- The Armv8-M architecture is the latest generation Arm architecture in the M-profile. It defines an architecture aimed at low cost deeply embedded systems, where low-latency interrupt processing is vital. It uses a different exception handling model to the other profiles and supports the T32 instruction set.