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About the MPU

The Memory Protection Unit (MPU) is a programmable unit that allows privileged software, typically an OS kernel, to define memory access permission. It monitors transactions, including instruction fetches and data accesses from the processor, which can trigger a fault exception when an access violation is detected.

The Protected Memory System Architecture (PMSA) is the architecture that defines the operation of the MPU inside the ARM processors. With the development of the ARMv8-M architecture, the PMSA has been updated to PMSAv8.

The MPU programmers’ model allows the privileged software to define memory regions and assign memory access permission and memory attributes to each of them. Depending on the implementation of the processor, the MPU on ARMv8-M processors supports up to 16 regions. The memory attributes define the ordering and merging behaviors of that region, as well as caching and buffering attributes. Cache attributes can be used by internal caches, if available, and can be exported for use by system caches.

ARMv8-M architecture with Main Extension have a dedicated Memory Management Fault (MemManage) that is triggered by accesses that violate the access permissions that are configured for an MPU region. The Main Extension also provides the MemManage Fault Status Register (MMFSR) and the MemManage Fault Address Register (MMFAR) which provide information about the cause of the fault and the address being accessed in the case of data faults. These provide useful information to RTOS implementations that isolate memory on a per-thread basis, or provide demand stack allocation.

If the MemManage fault is disabled or cannot be triggered because the current execution priority is too high, the fault is escalated to a HardFault. ARMv8-M implementations without the Main Extension can only use the HardFault exception.

If the ARMv8-M Security Extension is included, the Secure and Non-secure worlds have their own MPU. The number of regions in the Secure and Non-secure MPU can be configured independently and each can be programmed to protect memory for the associated Security state.

Certain memory accesses including exception vector fetches, accesses to System Control Space (SCS), which include MPU, NVIC, and SysTick, and the Private Peripheral Bus (PPB), which includes internal debug components, are not affected by the MPU settings. Also, the MPU configurations do not define the access permissions and attributes for debug accesses.

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