A64 Instruction Set
The A64 instruction set is supported by the Armv8-A architecture. Key features of A64 include:
- Clean decode table based on 5-bit register specifiers.
- Instruction semantics broadly similar to A32 and T32.
- 31 general-purpose 64-bit registers accessible at all times.
- No modal banking of general purpose registers for improved performance and energy.
- Program counter and stack pointer are not general purpose registers.
- Dedicated zero register available for most instructions.
What's new for Engineers in A64?
New instructions to support 64-bit operands
Most instructions support 32-bit or 64-bit arguments.
Assumes 64-bit address size
All addresses are assumed to be 64-bits in size. LP64 and LLP64 are the primary data models targeted.
Reduced conditional instruction set
The set of conditional instructions has been reduced down to cover branches, compares and selects only.
No arbitrary length load/store multiple instructions
Added LD/ST ‘P’ for handling pairs of registers.
For more details of the A64 instruction set, see the Arm Compiler armasm User Guide.