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Introduction to the ARMv8-M architecture

The ARM®v8-M architecture is used for the next-generation ARMv8-M processor family of real-time deterministic embedded processors. It is aimed at low cost deeply embedded systems, where low-latency interrupt processing is vital. The ARMv8-M architecture reduces the complexity of developing secure embedded solutions that scale all the way from the smallest IoT device to complex SoCs.

ARM uses the term architecture for the definitions of such things as the instruction set, programmers’ model and memory model, but not implementation details such as pipeline stages. Some of the features of the architecture, including parts of the instruction set, are optional.

ARMv8-M architectural enhancements enable better software design in several ways. For example, the new designs have a simplified programmers’ model for the MPU, so setting up a memory region is as simple as setting up a start and end address.

The ARMv8-M architecture provides enhancements to the debug components inside the cores. For example, the programmers' model for breakpoint and watchpoint units permits higher flexibility for breakpoint configuration and improved trace support.

The most significant enhancement in the ARMv8-M architecture is the inclusion of the optional Security Extension. The ARMv8-M architecture Security Extension can also be referred to as ARM TrustZone technology for ARMv8-M. TrustZone technology enables multiple security domains within a single processor system.

With existing ARMv6-M and ARMv7-M processor-based products, an application can execute various software components, such as communication stacks in an unprivileged state, and use the MPU feature to protect the system from memory corruption. In this way, even if the software stack suffers an attack and fails the rest of the system can still be functional because of the separation of stacks between privileged and unprivileged states.

While it is possible to create Secure embedded system designs with processors based on the ARMv6-M and ARMv7-M architectures, systems that require multiple applications or multiple security domains on a single Cortex-M series processor using these architectures can be challenging to design.

Some designs, such as complex SoCs, use multiple Cortex-M-series processors for system management and offloading I/O tasks. Of these, several processors can be in a permanent Secure domain, for example system management, and others in a permanent Non-secure domain, such as offloading of peripheral tasks. It is impractical to run the application entirely in unprivileged state as there are many restrictions on programs executing in this state.

TrustZone technology for the ARMv8-M architecture is designed to simplify such systems without the need for multiple processors, and can enable these systems to be built at lower cost.

The ARMv8-M architecture is a 32-bit architecture. The registers in the register bank, most data operations, and addresses are 32-bit. The 32-bit linear address provides 4GB of address space, which is architecturally pre-defined into several regions with different memory attributes.

Some portions of the memory space are used by the internal components of the processor core, such as programmable registers for:

  • Nested Vectored Interrupt Controller (NVIC).
  • SysTick timer.
  • System Control Block (SCB).
  • Memory Protection Unit (MPU).
  • Security Attribution Unit (SAU). Present only if the ARMv8-M Security Extension is implemented.
  • Debug components.

The rest of the memory space is utilized by chip designers in various ways. Architecturally there is no restriction on what type of memories or peripherals can be connected to the systems, so products from different chip vendors can all have different types of memories and peripherals.

Although the ARMv8-M architecture is 32-bit, it also supports data types of various sizes such as 8-bit and 16-bit. ARMv8-M also supports a limited set of 64-bit operations.

The architecture supports memory access instructions for various sizes, and there are instructions for converting between different data types.

Note

The ARMv8-M architecture does not support the A32 instruction set.

The instruction set supported by M-profile processors is the T32 instruction set, previously called the Thumb instruction set. It contains a range of 16-bit and 32-bit instructions. The ARMv8-M architecture only supports a subset of the T32 instruction set, with mostly 16-bit instructions. The ARMv8-M architecture with Main Extension supports a wider range of instructions, including an optional:

DSP Extension
A range of instructions including SIMD operations targeting DSP applications.
Floating-point extension
Which can be further divided into single-precision and double-precision, or single-precision only options.

Exception and interrupt handling are also defined by the architecture. In ARMv8-M processors, peripheral interrupts are a subset of exceptions. There are also extra system exceptions for:

  • Non-Maskable Interrupt (NMI).
  • Fault handling exceptions.
  • Software exceptions, for example, a Supervisor Call to the OS.
  • System Tick timer (SysTick exception).

The SysTick timer is a 24-bit built-in timer that can be used by the OS to generate periodic interrupts for task scheduling, or by application code for timing control.

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