Fault handling and detection
Error detection and correction techniques can be used to help mitigate the effect of errors in silicon devices. ARMv8-M processors include features that provide a means of detecting some of these errors.
In silicon devices, errors can occur because of:
- Software bugs.
- Usage errors, where the conditions are outside normal operational conditions. For example, temperature or supply voltage, or unexpected operations, such as invalid input data or operator errors.
- Memory corruptions, where stray radiation and other effects can cause the data that is stored in RAM to be corrupted.
Features of ARMv8-M processors can enable software to manage or even correct some of the error conditions, and alert the users of the device to the event so that corrective or protective actions can be taken. Some of the ARMv8-M devices are designed to detect more types of error conditions, and can handle the detected errors in a predictable manner, making them suitable for use in safety-related systems.
The features to detect and handle errors are divided into architectural features and implementation-specific features. The architecture for ARMv8-M processors incorporates fault handling features by exceptions, and a Non-Maskable Interrupt (NMI) for handling system level errors, for example, brown out detection. Implementation-specific features such as Error Correcting Code (ECC) for memories are not covered here.
The ARMv8-M architecture is designed for devices with a small silicon footprint.
In a similar way to the ARMv6-M architecture, all fault events are considered as unrecoverable. There are no fault status registers in the ARMv8-M architecture, as there are in the ARMv8-M architecture with Main Extension. However, software developers can still analyze errors during software development using debug features like the Micro Trace Buffer (MTB) or Embedded Trace Macrocell (ETM). These features provide recent execution history, and therefore enable issues to be identified easily.
It is also possible for silicon chip designers create their own fault status registers and fault address registers to capture information about bus errors.