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ARMv8-M Exception handling

An exception is any condition that requires the core to stop normal execution and instead execute a dedicated software routine that is known as an exception handler.

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Exceptions are conditions or system events that usually require remedial action or an update of system status by privileged software to ensure smooth functioning of the system. This is called handling an exception.

The ARMv8-M exception model describes how the processor responds to an exception, the properties that are associated with each exception, such as its priority level, and the exception return behavior. There is typically an exception handler that is associated with each exception type.

There are differences between ARMv8-M processors and other ARM processor families; for example, there are no IRQ or FIQ handling modes. ARMv8-M processors also have an integrated nested Vectored Interrupt Controller (NVIC), which identifies external interrupts to the core. This is unlike other ARM processors which have little direct hardware support for interrupts.

Hardware external to the processor core usually signals an interrupt, but there are several other events that can cause the core to take an exception, for example, internal events such as OS calls using the SVC instruction.

If the ARMv8-M Security Extension is implemented, it modifies some aspects of exception handling.

  • Some exception handling resources can be either Secure or Non-secure.
  • Some resources are banked (duplicated) to have both a Secure and Non-secure version.
  • Additional memory mapped registers are introduced in the System Control Space.
  • Additional bits are populated in some control and status registers.

The processor mode, states, and privilege level provide multiple possible combinations:

different_modes.png

The processor mode changes when an exception occurs in Thread mode, but does not change when an exception occurs in Handler mode.

To separate Secure and Non-secure stacks, processors that are based on the ARMv8-M architecture support four stack pointers if the ARMv8-M architecture with Security Extension is implemented:

  • Main Stack Pointers(MSP).
  • Process Stack Pointers(PSP).

In addition, a stack limit feature is provided using stack limit registers (accessible using MSR and MRS instructions) in Privileged level.

The following table summarizes the ARMv8-M architecture support for stack pointers.

Stack

Stack pointers

Corresponding stack limit register

Secure Main Stack - used by Secure handlers, and Secure thread.

MSP_S

MSPLIM_S

Secure Process Stack - used by Secure threads.

PSP_S

PSPLIM_S

Non-secure Main Stack - used by Non-secure handlers, and Non-secure thread.

MSP_NS

MSPLIM_NS

ARMv8-M with Main extension only

Non-secure Process Stack - used by Non-secure threads.

PSP_NS

PSPLIM_NS

ARMv8-M with Main extension only

The _S and _NS suffixes are used in the ARMv8-M architecture to identify whether the resource is for the Secure state or Non-secure state. Stack limit registers are available for all stack pointers in the ARMv8-M architecture with Main Extension. In the ARMv8-M architecture, the stack limit registers are available for Secure stack pointers only.

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The following sequence and figure show the possible stages in exception handling.

possible_stages.png

From Reset:

At reset all interrupts are disabled.

  • The core enters Privileged Thread mode (MSP).
  • An internal exception is taken:
    • Switch to Handler mode.
    • Run an exception handler.
    • Return to Privileged Thread Mode (Privileged +Thread+MSP).
  • Change from PT(Privileged +Thread) to UT(Unprivileged + Thread).

For an external exception.

  • Switch to Handler mode.
  • Run exception handler.
  • Exception handler is interrupted.
  • Reenter Handler mode
  • Service higher priority interrupt
  • Return to Handler mode.
  • Return to UT.
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